Rob Willoner, Intel’s strategic research manager of the Technology and Manufacturing Group would like to share the following papers that Intel is presenting at the Symposia on VLSI Technology and Circuits this week in Kyoto, Japan. The papers illustrate Intel’s relentless pursuit of improved performance, density and energy efficiency in current and future process technologies, circuits and SoCs. This work is designed to help improve devices’ performance, energy efficiency and overall usability.
Session 2-1: A 14nm SoC Platform Technology Featuring 2nd Generation Tri-Gate Transistors, 70 nm Gate Pitch, 52 nm Metal Pitch, and 0.0499 um2 SRAM Cells, Optimized for Low Power, High Performance and High Density SoC Products (Tuesday, June 16, 10:30 am) A leading edge 14nm SoC platform technology based upon 2nd generation Tri-Gate transistor technology has been
optimized for density, low power and wide dynamic range. 70nm gate pitch, 52nm metal pitch and 0.0499 mm2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore’s Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/mm, respectively, have been achieved at 0.7 V and 100 nA/mm off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are
0.50/0.32 mA/mm at 0.7 V and 15pA/mm Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.
Session 3-2: Variation-Tolerant Dense TFET Memory with Low VMIN Matching Low-Voltage TFET Logic (Tuesday, June 16, 1:30 pm) Computer chips, found in everything from the smallest ‘smart’ wearable accessories to enormous data centers, all need to reduce energy consumption. CMOS has dominated nearly 30 years of computing chip technology. A new transistor technology called TFET (Tunneling Field Effect Transistor) is a leading transistor research option that could improve energy efficient computation greater than 2X over CMOS. TFETs hold the promise of more environmentally-friendly data centers and mobile devices with longer battery life. This paper discusses technical advances that may allow the TFET to realize low voltage logic and memory and overcome nanoscale manufacturing challenges.
Session 11-2: High Sigma Measurement of Random Threshold Voltage Variation in 14nm Logic FinFET Technology (Thursday, June 18, 8:55 am) Microprocessors built using advanced logic technologies can contain a billion or more transistors on each die. Ensuring that each of these transistors works as expected is one of the key challenges in technology development. A low operating voltage is critical to reducing power. Of all the device metrics, random variation of threshold voltage (Vt) in transistors plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt random variation requires a large volume of measurements of minimum size devices to understand the rare event (high sigma) behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to Intel’s 14nm logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, with a well-behaved normal distribution out to +/-5 sigma.
Session 15-1: High-Performance Low-Leakage Enhancement-Mode High-K Dielectric GaN MOS-HEMTs for Energy-Efficient, Compact Voltage Regulators and RF Power Amplifiers for Low-Power Mobile SoCs (Thursday, June 18, 2:20 pm) This work investigates, for the first time, the use of GaN (gallium nitride) for realizing energy-efficient, compact voltage regulators and RF power amplifiers in low-power mobile SoCs. We fabricated a LG=90nm high-K dielectric enhancement-mode GaN transistor that showed low OFF-leakage, low ON-resistance, high drive current, and excellent power-added-efficiency at high RF output power density. These results provide significant improvements over industry-standard Si voltage regulator and GaAs RF power amplifier transistors, all at mobile SoC-compatible voltages. This work shows, for the first time, that the application space of GaN electronics can be expanded beyond the existing high-voltage power and RF electronics to include low-power mobile SoCs for improved battery life and user experience of mobile devices.
Session 3-3: A 12b 70MS/s SAR ADC with Digital Startup Calibration in 14nm CMOS (Wednesday, June 17, 11:20 am) Evolving wireless communication standards and devices continue to push for high data rates and low power. This translates to higher ADC (analog to digital converter) speed requirements in receivers at lower power targets. An architecture known as SAR is promising for low-power ADCs, but its speed and resolution have been limited. This paper presents a 12b 70MS/s sub-2 radix SAR ADC designed on Intel’s 14nm tri-gate CMOS process. The ADC incorporates a fully digital start-up calibration to correct capacitor mismatch errors to obtain high-resolution. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a CMOS-input pre-amplifier with clamped-outputs to achieve low-noise and high-speed operation. This novel SAR ADC achieves 68.1dB SNDR at Nyquist, 70MS/s speed, consumes 4.3mW power, and occupies only 0.019mm2 area.
Session 19-1: A 0.094um2 High Density and Aging Resilient 8T SRAM with 14nm FinFET Technology Featuring 560mV VMIN with Read and Write Assist (Friday, June 19, 10:30 am) Dual-port embedded memories are extensively utilized to provide high bandwidth and low-latency for high performance processor cores and graphics processing units on modern SoC designs. In this paper, we introduce a 14nm dual-port memory cell and array design featuring the smallest reported dual-port memory cell (0.094um2) and discuss bitcell and design choices that enable low voltage operation for power efficient operation. The array demonstrates operation at supply voltages below 560mV and achieves 1GHz operation at 0.6V, utilizing a delayed keeper read assist circuit and several write assist circuit techniques. High density, high bandwidth embedded memories extend an advantage to SoC products, allowing a reduction in die area for high performance processors and GPU cores.
Session 23-1: Broadwell: A Family of IA 14nm Processors (Friday, June 19, 1:55 pm) Intel Core™ M and 5th generation of Core processors (code named Broadwell) are fabricated on an optimized 14nm process technology resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 mV. Broadwell introduces the second generation of Fully Integrated Voltage Regulator (FIVR) with better droop control and parallel boot LVR (linear voltage regulator) mode added where-in rails are powered by LVR in deeper C-states to improve battery life . These features along with other power-reduction enhancements results in 35% reduction in active and standby power over first generation of FIVR. 3DL inductor technology, introduced for the first time in Broadwell, enables a 30% reduction in package thickness and improved low-load efficiency to increase battery life. IO re-partitioning of the SoC and a major re-design of DDR system resulted in a 30% reduction in I/O power. Shutting down various parts of the SoC die in various idle states (C* states) resulted in a 60% reduction in idle power. New software controlled co-optimization methods were implemented, such as duty-cycle control and dynamic display support, to improve the energy efficiency of the graphics and the display subsystem. Broadwell processor enhancements enable ≤9mm Fanless 2-in1’s for the first time on the Intel Core roadmap.
Session 26-1: A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, Bi-Directional, Quad-Lane Forwarded-Clock Transceiver in 22nm CMOS (Friday, June 19, 5:55 pm) Continually improving display and camera resolution in mobile platforms demand high bandwidth I/O links to the processing unit. This increased bandwidth requirement can be sustained only by lowering the I/O link power dissipation. Furthermore, to reap the benefits of CMOS scaling (lowered area and power dissipation), the I/O must be highly digital for easy portability from one process node to another. In this paper, we present a highly digital, low power I/O interface targeting mobile platforms. The quad lane transceiver implemented in 22nm CMOS operates between 3-to-8 Gb/s/lane at 0.5-to-0.75V with energy efficiency ranging between 385-to-790 fJ/b. A source shunt terminated transmit driver with implicit supply noise rejection and all digital deskew help realize I/O operation at very low supply voltage (0.5V) and enable a sub pJ/bit link with fast wakeup capability.
Session 26-3: A 1.2-5Gb/s 1.4-2pJ/b Serial Link in 22nm CMOS with a Direct Data-Sequencing Blind Oversampling CDR (Friday, June 19, 5:05 pm) High-speed I/O links for mobile applications like notebooks, tablets and smartphones demand good energy efficiency in active mode, and the ability to quickly transition between active and standby modes to save power. Furthermore, a digital-intensive design that is amenable to fast time-to-market and occupies low area is highly desirable. For applications like MIPI (mobile industry processor interface), the link must also have an ability to operate in a single lane with minimal power penalty. Most conventional CDR (clock and data recovery) techniques utilize feedback which restricts the capability to quickly acquire lock when transitioning to an active state. This paper presents a data-rate-scalable digital-intensive link with a direct data-sequencing blind oversampling CDR to meet the aforementioned demands. This bidirectional link consists of a transmitter, receiver and two all-digital phase-locked loops without utilizing any analog circuitry and achieves a 14X area reduction, and 3X efficiency improvement over comparable links. The link occupies an area of only 0.041mm2.
Session JFS3-3: Low-Voltage Metal-Fuse Technology Featuring a 1.6V-Programmable 1T1R Bit Cell with an Integrated 1V Charge Pump in 22nm Tri-gate Process (Thursday, June 18, 3:10 pm) Metal-fuse PROM (programmable read-only memory) continues to serve as the embedded memory technology responsible for providing functions such as die identification, cache repair and adaptive circuit tuning. In-field fuse programming has recently gained popularity as it can enable end-user feature customization. Low-voltage fuse technologies improve the product competitiveness for such applications by maintaining compatibility with standard power supply rails which allows integrated power delivery solutions that reduce platform costs. This paper demonstrates the second-generation high-volume metal-fuse technology with continued scaling to 22nm tri-gate CMOS. An array architecture featuring a 16.4µm2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. The low voltage programmability enables the on-die integration of a charge pump voltage doubler for in-field programming applications operating on a 1V logic supply rail. The technology also features a 2.05µm2 1T1R bit cell for high-density applications.