World-Changing Technology to Enrich People’s Lives: Architecture Day 2020, the Six Key Intel Technology Pillars, and Intel® FPGAs

Earlier this month during Architecture Day 2020, Intel’s Chief Architect Raja Koduri and a dozen Intel fellows and architects discussed numerous advanced technologies that the company has developed and is developing so that it can continue to deliver solutions for our customers’ greatest challenges. These many advanced technologies comprise the six key pillars of innovation that collectively embody the focus of the company’s engineering development work:

  • Process and Packaging
  • XPU Architecture
  • Memory
  • Interconnect
  • Security
  • Software

All six of these pillars are essential to creating the solutions that fuel Intel’s purpose: To create world-changing technology that enriches the lives of every person on earth.

Perhaps the most broadly discussed of these six pillars is semiconductor process technology; That technology pillar has certainly been an Intel crown jewel for more than half a century. During Architecture Day 2020, Ruth Brain, Intel Fellow and Director of Interconnect Technology and Integration at Intel, discussed the company’s new 10nm SuperFin technology, which represents the largest single intranode process technology enhancement in the company’s history. Intel’s 10nm SuperFin process technology delivers performance improvements comparable to a full-node transition by incorporating several innovations including:

  • An improved finFET gate process that results in higher electron mobility and faster transistors
  • Self-aligned quad patterning, which nearly doubles the scaling density of the critical M0 and M1 layers in the metal stack
  • Cobalt local interconnects, which halve via resistance and reduce electromigration by a factor of 5X to 10X
  • COAG (contact over active gate) design, which further reduces cell size and improves transistor density by relocating the finFET’s gate contact from its previous location next to the transistor to a spot directly over the transistor’s gate, thus reducing the amount of real estate consumed by each transistor

These and other innovations in the Intel 10nm SuperFin process technology demonstrate that feature size is not the only significant parameter when it comes to improving performance.

In a nearly prescient article titled “No More Nanometers” published only a couple of weeks before Architecture Day 2020, EEJournal’s Kevin Morris describes the essence of the Intel six-pillar strategy when he wrote:

“For the previous three decades, there was little reason to optimize … anything, really. After all, why spend a huge amount of energy doing a 15-20% improvement that would simply be obliterated by the 2x bounty of the next Moore’s Law node, and another 2x two years after that? We simply focused on building the functionality we needed and relied on lithography progress to make it faster, cheaper, and more power efficient. Now, however, we engineers couldn’t just ‘phone it in’ anymore. We had to come up with new and novel ways to improve performance and reduce power consumption, rather than relying on the penumbra of Moore’s Law to get us past the finish line in our system designs.”

In a follow-on EEJournal article titled “Intel – Flourish or Flounder,” which also appeared before Architecture Day 2020, Morris wrote:

“The big gains in process technology have been from innovations such as finFETs and other advances that don’t relate to geometry shrinks.”

This sentence succinctly describes the approach taken in the development of Intel’s 10nm SuperFin process technology. (Note: Morris’ opinions as expressed in his second article firmly fall on the “flourish” side of its headline’s implied question.)

Press and analyst reaction to the Architecture Day 2020 discussion of the 10nm SuperFin process improvements has been very positive. Here are a few quotes:

“Intel’s improvements in the 10nm process and architecture are so significant that the company is claiming a nearly 20% performance improvement over 14nm. With 14nm, Intel made small incremental performance improvements of roughly 4-5% per refresh (+++), which amounted to about 20% across four different CPU architectures. Intel is achieving this with a single step rather than four, which is what makes this transition to 10nm much more significant than many realize.” – Patrick Moorhead, Forbes

“Pursuing more cost-effective methods of interconnection and aggregation is how we’ll drive down the cost of mounting memory closer to the CPU and improving overall performance characteristics. The work Intel is talking about on the interconnect front is critical to long-term performance improvements and better power efficiency.” – Joel Hruska, ExtremeTech

“Intel’s advanced packaging technologies will allow it to mix and match IP and process nodes from other vendors into the same heterogeneous packages, yielding time to market advantages.” – Paul Alcorn, Tom’sHardware

“In terms of the wrap-around process, with the support of architecture and technology, Intel’s 10nm is far more powerful than imagined, and the final judgment standard still needs to be based on the performance of the whole set.” – Fu Bin, 21ic Electronic Network

However, semiconductor process technology constitutes only part of the first Intel technology pillar. Packaging technology constitutes the other part – a co-equal part – of the pillar.

There are big performance, power, and cost gains to be achieved from packaging improvements. That’s why the next Architecture Day 2020 talk – presented by Ramune Nagisetty, Senior Principal Engineer and Director of Product and Process Integration at Intel – discussed several of the many packaging innovations that Intel has developed, including:

  • EMIB (Embedded Multi-die Interconnect Bridge) and AIB (Intel’s Advanced Interface Bus), which are used to combine several semiconductor die in one package using 2.5D packaging technology
  • Foveros technology, which extends chip packaging into the 3rd dimension
  • Hybrid bonding, which further improves 3D chip packaging
  • Co-EMIB, which blends 2D, 2.5D, and 3D packaging techniques to enable the creation of a larger-than-reticle sized base with high-density connections among companion die and stacked-die complexes

Intel has used the EMIB and AIB packaging technologies for heterogeneous integration in FPGA development for several years. The Intel® Stratix® 10 and Intel® Agilex™ FPGA families employ heterogeneous packaging as a foundation technology to combine FPGA base die with a variety of advanced I/O die to add features such as 116 Gbps SerDes transceivers, PCIe Gen5 ports, and UPI and CXL coherent processor attach ports. Heterogeneous integration is also a key technology used in the creation of the Intel Stratix 10 MX FPGA, which adds high-speed HBM2 memory die stacks to the mix.

Intel’s advanced packaging technology makes it possible to create broad, diverse product families and bring them to market quickly. For example, heterogeneous integration accelerated the development and recent introduction of the newest member of the Intel Stratix 10 FPGA family – the Intel Stratix 10 NX FPGA – which changes out the existing FPGA die in the Intel Stratix 10 MX FPGA with a newly designed FPGA die to produce an AI-optimized FPGA. The new FPGA die replaces existing DSP blocks with AI Tensor blocks, tailored for the computations needed in AI workloads. The result was a 15X performance boost for these workloads. Heterogeneous integration allowed Intel to bring the Intel Stratix 10 NX FPGA to market more quickly than might have been possible otherwise and opened a new market segment for Intel.

Intel FPGAs are certainly not the only products in Intel’s silicon portfolio to benefit from the company’s advanced packaging technologies. For example, Intel® Core™ Processors with Intel Hybrid Technology, code-named “Lakefield,” were announced in June. These new members of the Intel Core processor family are the industry’s first product to incorporate Intel’s Foveros 3D stacking technology and a hybrid computing architecture.

During Architecture Day 2020, Ravi Kuppuswamy – Corporate Vice President and General Manager of Custom Logic Engineering – disclosed that Intel’s next-generation FPGAs would employ both Foveros and Co-EMIB packaging technologies. Kuppuswamy also disclosed a new SerDes test chip, which currently operates at 112 Gbps in NRZ mode and 224 Gbps in PAM4 mode. This new SerDes represents precisely the sort of semiconductor chiplet technology that requires advanced packaging technologies such as Foveros and Co-EMIB to become practical.

The critical importance of advanced packaging and heterogeneous integration is not lost on the press and analysts. Here are some observations from various publications, based on the information presented during Architecture Day 2020:

“Intel’s advanced packaging technologies will allow it to mix and match IP and process nodes from other vendors into the same heterogeneous packages, yielding time to market advantages. The standardized AIB (Advanced Interface Bus) interface is the key that unlocks that level of cooperation and integration between so many disparate partners. Intel has worked to further this once-proprietary standard by contributing it to the open-source CHIPS alliance without requiring royalties or licensing, thus allowing other companies to develop chiplets that are compatible with both Intel and others’ chiplets.” – Paul Alcorn, Tom’s Hardware

“Related to the future of design and packaging in the industry, which I see as chiplets from many companies coming together in a 3D package, I feel confident Intel is extremely competent, maybe even the current lead. This is a long-term strategy and industry shift… Intel’s commitments to improving packaging and IO are among some of the most impressive ways that I see them navigating this new competitive environment and should yield some very interesting products down the road…” – Patrick Moorhead, Forbes

“Intel detailed that the EMIB roadmap, with its AIB or Advanced Interface Bus architecture, will scale to a much denser 36 micron bump density and up to 6.4Gbps wire data rate with AIB 2.0. In addition, Intel has made an AIB Generator open source and available on GitHub, to help enable ecosystem partners to develop on the technology as well. Intel calls this “2.5D” packaging technology…” – Dave Altavilla and Marco Chiappetta, HotHardware

“What I will say is that if this is truly Intel’s direction, then defining this strategy and building the chiplet ecosystem could be, by far, the most important job at the company.” – Patrick Kennedy, Serve the Home

Process and packaging technologies are not all that’s needed to reach the sort of goals that Intel aims to achieve in the quest to move, process, and store everything. Computing workloads have been changing, expanding, as the world finds new ways to harness computing technology. That’s why the XPU architecture concept is the second of Intel’s technology pillars.

Intel has characterized four broad computing architectures for the XPU architectural pillar:

  • Scalar: As characterized by the many Intel CPU and processor families
  • Vector: As characterized by the Intel® Xe family of GPUs (extensively discussed during Architecture Day 2020)
  • Matrix: As characterized by the Intel® Habana® Gaudi® and Goya™ AI processor families
  • Spatial: As characterized by Intel FPGA families

All of these processing architectures are important in the quest to turn mountains of raw data into usable information and all exist within the Intel semiconductor portfolio. To convert these mountains of data into useful, actionable information, future software programmers need a unified programming environment, architecture, and languages that natively support these four basic computing architectures. That’s why another of the Architecture Day 2020 presentations was devoted to oneAPI, which is Intel’s company-wide effort to develop the unified set of tools needed to deploy applications and solutions across these four computing architectures.

We’ll give EEJournal’s Kevin Morris the last word here, from his article titled “No More Nanometers”:

“…to really evaluate a semiconductor technology platform, we have to look well beyond the number of transistors we can cram on a monolithic piece of silicon. We need to look at all the elements that define system-level performance and capability and account for all of those. Beyond the usual performance, power, and area of monolithic silicon, we have packaging technology that allows us to stack more (and more varied) die in a single package, interconnect technology that improves the bandwidth between system elements, architectural and structural improvements to semiconductors that are not related to density, new materials that improve the speed and power efficiency – the list goes on and on.”

 

If you’d like to watch the Architecture Day 2020 presentations for yourself, the full video presentation lasting nearly three hours is available here in the Intel Newsroom and the 233-page slide deck used during the presentation is available as a PDF here.

 

Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge.

 

 

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Published on Categories Acceleration, Agilex, AIB, Chiplets, EMIB, oneAPI, StratixTags , , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.