New article discusses why FPGAs are a good choice for deep-learning applications and research

Many AI workloads such as image recognition rely heavily on parallelism to achieve good performance. For that reason, early AI researchers swiftly adopted GPUs, which provide significant amount of computational parallelism. GPUs were originally designed to render video and graphics, so they excel at parallel processing and can perform a very large number of arithmetic operations in parallel. GPUs deliver incredible acceleration for cases where the same computations must be performed many times in rapid succession. However, GPUs have their limits and can’t deliver as much performance as an AI-specific ASIC purpose-built for a given deep-learning application. ASICs are limited in a different way, because of their high non-recurring engineering (NRE) costs and long development cycle, which can be anywhere from 12 months to years for development, verification, and fabrication.

FPGAs offer ASIC-like hardware customization and can be programmed to deliver performance similar to a GPU or an ASIC for AI workloads but with speedy development cycles. The FPGA’s reprogrammable, reconfigurable nature makes FPGAs well suited to the rapidly evolving AI landscape. FPGAs allow designers to test algorithms quickly and get to market faster with a high-performance solution.

A new article titled “FPGA vs. GPU for Deep Learning” explores these topics in detail. The article discusses the unique advantages FPGAs enjoy for deep-learning applications. It also discusses the unique FPGA-related offerings from Intel including:

 

 

Click here to read the article.

 

For more information about the AI-optimized Intel Stratix 10 NX FPGA, see “Intel has just announced its first AI-optimized FPGA – the Intel® Stratix® 10 NX FPGA – to address the rapid increase in AI model complexity.”

 

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Published on Categories AI/ML, StratixTags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.