IPAS: Intel Debug Technology

Hi everyone,

In a previous post, we provided some high level information about Intel debugging tools. Today we are going deeper with the publication of the Intel Debug Technology technical paper that focuses on Intel® Debug Protection Technology and debug capabilities within Intel hardware.

Debug is a critical capability, not just in Intel hardware, but of any system in order to get it from manufacturing, to production, to deployment.  As the paper describes, where Intel differentiates itself in the industry is not only in our willingness to be transparent about these technologies, but also in our efforts to help define and adopt industry standards.

Enrico Carrieri, one of the authors of the paper joins myself and my colleague Christopher (CRob) Robinson in the video below. Enrico is a Senior Principal Engineer in the Debug Architecture and Ramp Enabling (DARE) team based out of Folsom, CA.  A 22-year veteran at Intel, he started as an analog engineering intern and moved into digital design and later lead debug architecture, design, and validation teams.  Enrico has worked on many of Intel’s products including those in Flash memory, chipsets, mobile devices, and recently in client and server.  As part of the DARE team, Enrico owns the corporate debug interfaces architecture and strategy and leads the debug security and privacy solutions strategy for the Intel® Debug Protection Technology.

Outside of Intel, Enrico chairs the MIPI Alliance Debug Working Group and has been a technical contributor on some of the MIPI Alliance’s latest specifications including the Narrow Interface for Debug and Test (NIDnT), I3C Basic, Debug for I3C, and the SneakPeek Protocol specifications.  He started what is now the Security WG in the MIPI Alliance and is an active participant authoring specifications. Enrico was also part of the USB Type-C Debug Accessory Mode definition from the USB-IF.

Enrico holds several patents and has patents pending on topics such as power savings, I3C, debug, and security (with a patent pending specifically on debug security architecture). He holds a BS in Electrical Engineering and a BS in Computer Engineering from Penn State.

This paper demonstrates Intel’s strategy for the protection of sensitive assets and describes privilege levels from Intel debug mode, those available to systems manufacturers, on up to those available to anyone. This aligns with our Security-First Pledge.  We not only want customers to be educated and better understand our protection mechanisms, but to also engage with us on future developments in this area.

Thanks to Enrico and the DARE team for sharing the strategy and for continuing to share their expertise across the industry to help advance security and privacy for everyone!

Jerry Bryant
Sr. Director
Intel Product Assurance and Security

Published on Categories Security
Jerry Bryant

About Jerry Bryant

Jerry Bryant is a Senior Director of Security Communications at Intel Corp. where he leads communications strategy, vulnerability issues management, field, and customer readiness within the Intel Product Assurance and Security Group (IPAS). Jerry has over 20 years experience in product security incident response within fortune 50 companies and specializes in vulnerability handling, incident/crisis management, threat intelligence sharing, industry, and government engagement. He believes strongly in sharing lessons learned and helping to advance the knowledge and readiness of defenders across the industry. Jerry is a co-author of the Product Security Incident Response Team (PSIRT) Services Framework, a cross industry collaboration through the Forum for Incident Response and Security Teams (FIRST.org).