SPIE’s annual Advanced Lithography conference is underway, and as Intel’s Britt Turkot, senior principal engineer in Logic Technology Development Lithography, described in her keynote, significant strides have been made in EUV lithography over the past year taking the technology from a question of if to a question of when. EUVL is solidly on a path to HVM insertion as soon as the technology becomes ready and it is cost effective.
Turkot talked about EUV progress made at Intel and identified the areas that require the most attention, these being the scanner and masks.
For the scanner, EUV source power and predictable system availability are critical. EUV source power, a key enabler of throughput, has been improving steadily. There are now multiple tools around the world running in 80 watt configuration, versus just one a year ago. The lifetime and reliability of the droplet generator, used to create microscopic tin droplets which are then struck with a high power laser to produce EUV light, have improved significantly over the past year. Intel is seeing combined scanner and source availability (4-week rolling average) exceeding 70%, providing good wafers per week capacity that is now sufficient for technology development. Turkot also showed encouraging data from Intel’s 14nm pilot line demonstrating EUV process capability. She showed good overlay trends, stable critical dimension uniformity over 7 months and good electrical testing and EOL yield results. Turkot emphasized the need to keep momentum on all these fronts going forward.
With regard to EUV masks, defectivity is key. Turkot reported an improving trend of multi-layer defectivity. She also showed successful defect mitigation strategies on multiple devices, and a robust e-beam pattern defect repair capability. She also talked about the need for a pellicle in the scanner to protect the mask and Intel’s collaboration with ASML to enable this new capability. The results have progressed from small “coupon” lab samples to the significant achievement of demonstrating 200+ wafer exposures with a full size pelliclized reticle in a scanner at Intel. Turkot stated that the basic tool capability exists today to support pellicle membrane materials development and quality control, but, defectivity levels on pellicle membranes are still high, and availability of quality pellicle membranes is the highest risk to timely EUV pellicle implementation. Inspection of pelliclized reticles is also needed to ensure predictable yield. She said that APMI (actinic patterned mask inspection) is not a show-stopper, but without it, yield and cost may be an issue. Yield improvement, cost control, and ecosystem development will be the focus areas in EUV mask fabrication.
The road to EUV lithography production is a long one. While there has been great progress, much work remains to realize this magic in manufacturing. Technology development requires rapid information turns, so high tool availability, enabling running wafers without delay, is our critical and gating concern today.
This is a very exciting time for semiconductor process technology. It has been over half a century since Intel’s co-founder Gordon Moore stated his famous “law”. Intel has a full pipeline of technology options, of which EUV is a very big one, giving us full confidence in the continuation of Moore’s Law for the foreseeable future.
Janice Golda is director of Lithography Strategic Sourcing in the Technology and Manufacturing Group at Intel.