A sneak peek at chips of the future

What IS IEDM? IEDM stands for the International Electron Devices Meeting, and it is THE international forum for nanoscale device technology. Papers at this forum represent the “best-of-the-best” in device accomplishments for the calendar year. 1400 people attended the conference, with an acceptance rate for papers of ~35% (and that includes the invited papers!) The forum oscillates in location between San Francisco and Washington DC, and this year it was in Washington DC.

One of the first impressions one gets in attending IEDM is how much Intel is held up as the “target to beat”. This was particularly apparent in session 9 (Circuit and Device Interaction – Advanced CMOS Technology Platforms) where the major players in the industry not only benchmarked their data against ours, but even used similar graphics and format as our presentations. (The quote “Imitation is the most sincere form of flattery” springs to mind in this forum!) A great example was TSMC’s 16nm FinFET paper, which was benchmarked (virtually graph for graph) against our 22nm technology (VLSI 2012, Chris Auth, et al. and IEDM 2012, Chia-Hong Jan, et al.).

Another fascinating thing about session 9 was the increasing emphasis on parts of the system beyond the device itself. Intel, for example, presented a very well-received paper (Eric Wang, et al.) on a capacitor-over-bitline eDRAM implemented on 22nm Trigate (see Fig. 1). Eric, the primary author, did a nice job in moving beyond the device to focus on device-circuit interactions, showing that implementation of noise reduction circuit techniques and extensive device and design co-optimization could provide over 100μs retention time at 95°C in a Gbit eDRAM. (This paper also demonstrated one of the characteristics of Intel papers at IEDM, which is for the room to dramatically fill up with people before an Intel paper, and then empty again after the paper is completed.)


Fig. 1. The Capacitor-over-bitline (COB) eDRAM architecture discussed in Eric Wang’s session 9 Intel paper.

Device-circuit interactions were also the theme of the Intel invited paper (Greg Taylor) which led off session 17 (Circuit and Device Interaction – Analog and Mixed Signal Circuit/Device Interactions). Greg discussed the challenges of implementing analog and mixed signal circuits on process technologies that have been optimized for logic performance (always a hot button in this community!). One of the points he made was the importance of moving as much circuitry as possible to the logic device and focusing device development energy only on those devices/circuits which cannot be made using logic. Greg also pointed out the possibilities for leveraging challenges as benefits (something I instantly named “Aikido Analog”) and gave an example of an analog to digital converter that benefits from increased device variation.

Intel had a very strong presence this year in the novel devices community, with two well-received papers on tunnel FETs (TFETs) and a fascinating paper on some fundamental science in GaN devices.

TFETs are electron devices which operate by tunneling through the source-drain energy barrier (rather than by hopping over the barrier as in a conventional MOS device.) As a consequence of using tunneling, they have better sub-threshold slope than MOS, and thus a potential for better performance at low energy/power operating points. Intel had two TFET papers this year, one in session 4 (Nano Device Technology – Steep Slope Devices) and one in session 33 (Circuit and Device Interaction – Circuit/Device Variability and Reliability). In the Session 4 paper (Uygar Avci and Ian Young), Uygar introduced an innovative new device (called a resonant tunnel FET) which creates a narrow triangular potential well at the source side of the heterojunction possessing discrete resonant energy levels. If these resonant levels can be designed to align with the source valence band when the device is on, then a significantly steeper subthreshold stope can be obtained (see Fig. 2). In the session 33 paper (Uygar Avci, et al.), Uygar discussed the impact of variations on TFET devices when compared to conventional MOS devices, and predicted a 64% average energy savings against Si CMOS at Lg=13nm.


Fig. 2. Improvement of the resonant tunnel TFET over a conventional TFET and MOS device as shown in Uygar Avci’s session 4 Intel paper.

It is rare in our business to be able to show entirely new physics to the transistor community. However, this year, we were successful with a paper in session 28 (Power and Compound Semiconductor Devices – Next generation logic and power). In this paper (H. Then, et al.) Han discussed the observation of a “negative capacitance” effect in an AlInN/AlN/GaN MOS-HEMT. He pointed out that negative capacitance effects (interesting to us because they result in improved subthreshold performance, similar to a TFET) have been predicted theoretically, but not in the GaN system and not with this particular type of physics. You can imagine that the question period for this paper was quite vigorous, with various physics experts torn between disagreeing with our interpretation but being impressed and intrigued by our data!

Last, but certainly not least, were the panel sessions. Intel’s Kevin Zhang chaired the session on “Will Voltage Scaling in CMOS Technology Continue Beyond the 14nm Generation?” and I was one of the panelists. I can certainly say that Kevin’s session was an exciting one, beginning with the dramatic proposal by IBM’s Tak Ning for a return to bipolar and ending with my (probably less dramatic, but likely more practical) observation that design-process collaboration seems to be the key for CMOS scaling past 14nm IBM’s Jeff Welser chaired the session on “Is there life beyond conventional CMOS” and Ian Young was one of the panelists. In this session, panelists both proposed the steep slope (Tunneling FET, Ferro-electric FET, Metal Insulator FET) devices and the spintronics devices (All-Spin Logic) as the likely front runner devices beyond conventional CMOS. Several panelists stated these devices must provide power-performance benefit at the functional block and system level, where Beyond CMOS devices will not replace CMOS but will augment it (i.e. “Beyond CMOS” will “Be-On-CMOS”). Ian made the point that a new device may only come about if it enables new applications – not just be about replacing CMOS. One strong option for this is heterogeneous integration of CMOS and Beyond CMOS devices to more optimally implement the functions in the SOC.

Overall, the conference “trend” was upbeat – with lots of energy showcasing technologies of value to the mobile and SOC communities. Still no end in sight for Moore’s Law!