Enforcing Moore’s Law through Technology Research – Part 5B

by Mike Mayberry, Vice President, Technology & Manufacturing Group, and Director, Components Research

Welcome to part two of the fifth installment! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities. See last installment and links to the others.

In the last blog, I talked about optimizing materials to get higher mobility and optimizing the structure to get to better coupling. Still a third optimization direction is to look at different types of device operation, particularly as we try to make very small devices. Look once again at the devices shown in figure 1.

Fig 1: Generic diagram of QWFET structure compared with MOS



These are P-channel devices with source (input) and drain (output) made of complementary N-type materials. When no voltage is applied, only leakage current flows, and when the gate voltage is high enough the channel inverts and becomes conductive.

Figure 2 shows the three possible optimization directions: materials, coupling, architecture.

Fig 2: A device can be optimized for performance in multiple ways: better materials to improve charge mobility, improved field coupling, and different (better?) modes of operation.

In the first example, JAM is a junction-less accumulation mode device [Ref. 1]. It consists of a uniformly doped single block of material, for example all N-channel. The gate structure is oppositely doped, for example P-type in order to make the device normally off. As the gate voltage is increased, it offsets the built-in field from the gate doping and allows the device to turn on. The promise of this device is lower electric field (with the potential for improved mobility due to reduced surface scattering) and potentially better scaling.

In the second example, the traditional semiconductor source and drain regions are replaced with metals which place the ends of the channel at different voltage points [Ref. 2]. The promise is very low contact resistance to the channel and immunity to some sources of variation. The challenge with metal source-drain devices is that the metals (one for the N device and one for the P device) must have tuned work-functions to place them at the right reference level. That becomes a significant materials challenge.

The third example, the tunneling field effect transistor (TFET) is the subject of a modeling paper presented at the June 2011 VLSI Symposium in Kyoto, Japan [Ref. 3]. Unlike a conventional device, a TFET has an undoped channel and source/drain regions of opposite polarity (Fig. 3). In a conventional device, the gate voltage lowers the barrier to produce a conductive channel. In a tunnel FET, conduction occurs by tunneling between the valence (bottom curve, fig. 3) and conduction (top curve, fig. 3) band barrier and flow is modulated by the width of the barrier and the presence of entry and exit states. It turns out that conduction in this device can be a very steep function of the applied voltage meaning the device can turn on and off with a much smaller voltage swing compared with conventional CMOS.

Fig 3: A TFET operates by tunneling between the barrier formed by the valence and conduction bands and current flow is modulated by the width of the barrier and the presence of entry and exit states.

There is no free lunch here though. The bands have to be very precisely placed with respect to one another to create the correct tunneling behavior and a choice of different compound semiconductor materials allows us freedom to move the bands to the desired points. Still at the small dimensions considered here, we are strongly in the realm of quantum mechnical behavior, and the precise band position is a function of channel dimensions. We used a simulator that models the coupling behavior of individual atoms in order to correctly model the device and then explored how to optimize the behavior. This is more efficient than building a hundred different variations and measuring to see which one works best.

Fig 4: Two possible InAs double gate TFET configurations differing in placement of the drain region compared with scaled CMOS.

In the case of the blue curve, there is high band to band tunneling even when the device is supposed to be off and this device is much worse than conventional CMOS. For the red curve, further optimization has reduced the off current while preserving the steep turn-on. As you can see the red curve turns on faster than the conventional CMOS device and has better performance for voltages below 0.3V while above that threshold, conventional CMOS is better. We might use a device like this in a product as part of an always on sensor/detector. When something interesting happens this circuit wakes up the rest of the device to do something requiring higher performance. It would have substantially better power-performance in this regime; we are estimating 8x better.

We are in the process of building variations of TFET devices and are working to demonstrate they work as well as predicted. Then this becomes one of the many choices we have to make to optimize our future transistor technology.

Ref. 1: JAM, J.P Colinge (Tyndall), Nature Nanotechnology, 2010

Ref. 2: Metal S/D, Larson (Spinnaker) TED 2006

Ref. 3: “Comparison of Performance, Switching Energy and Process Variations for the TFET and MOSFET in Logic,” Intel, VLSI Symposium 2011

4 Responses to Enforcing Moore’s Law through Technology Research – Part 5B

  1. Kevin says:

    Very interesting Article and a good read. I freely admit I am an incredible novice when it comes to the broad spectrum of devices and device computing in general, however I do have one question: Due to the potential costs and limitations with Graphene, especially when considering 3rd order devices, has Intel started experimenting with electro-optical polymers?
    Thanks in advance!

  2. Mike Mayberry says:

    I assume you are referencing eletrical-optical computing elements. In general since our devices are 100-1000x more dense than the equivalent optical element (light wavelength is too long!), optical computing as a replacement for electronic computing is not particularly attractive. We are currently looking at transducers to convert from one domain to another and there might be exotic special purpose functions where you don’t convert between domains that might be interesting in the future.

  3. Kevin says:

    Mike, thank you very much for your prompt response. Like I said, I’m a newbie, so perhaps I didn’t understand as much as I thought I did, or perhaps I did not word my question appropriately (both would be a strong possibility!). Let me try to rephrase…On the last segment, 5-A, you mentioned the possible use of other materials to (gallium arsenide, as one)further technology and speed. It is my understanding that there are polymers being researched/made that could potentially be utilized in conjunction with silicon (silicon photonics?)to create hybrid devices using standard the CMOS processes. I guess that is what I was referring to in my previous post. I was just wondering your thoughts on that.
    Thanks, and sorry if I am way off!

  4. Mike Mayberry says:

    Thanks for clarifying. There are materials under investigation for optical modulators (electrical to optical transducers) which I mentioned above and there are separate classes of material for solar (optical to electrical conversion) and for organic electronics (no optical involved). In general, the organic electronics have much lower conductivity and/or mobility and so are potentially useful for low performance printed electronic applications but not in the space we’re discussing in this blog.