Enforcing Moore’s Law through Technology Research – Part 5A

by Mike Mayberry, Vice President, Technology & Manufacturing Group, and Director, Components Research

Welcome to the fifth installment! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities. See: last installment and links to the others.

In the last blog I hinted that our list of challenges was only a starting point and so in this installment I’ll give some explanation about other considerations. First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). The key advantage of these materials is high charge mobility. Mobility is a measure of how easily you can move charges within the material with application of an electric field. Higher mobility can produce faster devices and/or devices that require much less power. Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. Our goal is to take advantage of the vastly larger spending on silicon infrastructure and put it to use fabricating compound semiconductor devices.

Here’s a diagram comparing a compound semiconductor quantum well (QW) device on left with a conventional silicon device on the right. In this cartoon the challenge becomes how to fabricate that very thin QW layer and to integrate all the materials in a compatible manner.

Fig 1: Generic diagram of QWFET structure compared with MOS

Past research work has shown that we can integrate the materials and get very high performing devices but so far we can make still smaller devices with conventional silicon. Generally speaking to make very small devices that also perform well, you need to decrease leakage paths that limit your ability to turn off the device and minimize resistance when the device is on. So for the moment, assume the fabrication challenges of the blue QW in figure 1 are solved and focus on what else is required.

One aspect is the ability to couple the electric field of the gate (G) to the channel (QW). Tight coupling can be achieved by effectively moving the gate closer to the channel (high k dielectrics), thinning the channel (fully depleted devices), or add additional gates (finFET’s and other multi-gate devices including trigate). Here’s a cartoon to illustrate these three directions.

Fig 2: Tighter coupling can be achieved by moving the gate closer, limiting the channel thickness, or adding electric field from more than one side.

And here are some actual structures showing optimization by adding extra directional control, partially fabricated to make it easier to visualize.

Fig 3: A tall thin fin of Indium Gallium Arsenide with a capping layer, an equivalent fin structure with gate added, and finally an individual nanowire made from Germanium. The control gate(s) can be on either side of the fin for left two or wrapped around the wire for third case.

In the left hand fin, adding a gate (center) will mean the channel sees the electric field from two sides while in the right hand wire, the gate would surround the channel on all sides. The latter, gate all around (GAA), represents the highest possible coupling for a given gate dielectric but is of course the hardest to build. These can get quite complicated in three dimensions as illustrated in Fig 4.

Along the horizontal axis we have:

  1. Ultra thin body (UTB) on silicon on insulator (SOI) which corresponds to middle diagram of fig. 2. Gate control is from just the top.
  2. Fins which correspond to right hand side of fig. 2. Gate control is from two sides or two sides and top.
  3. Wires which have gate control from all sides.

Fig 4: A device can be optimized for performance in multiple ways: better materials to improve charge mobility, improved field coupling.

You may have noticed a big white space on fig. 4. That third direction will be the subject of the next blog and is yet another reason that compound semiconductors are interesting.

2 Responses to Enforcing Moore’s Law through Technology Research – Part 5A

  1. Saurabh Sinha says:

    Really interesting article, though I would have preferred more technical details or references to related papers. Can you provide a high-resolution image for Fig.4, The top figure (III-V) block cannot be clearly seen?
    So after FinFETs, the next thing that might help us move forward will be FinFETs with III-V QW channels?

  2. Mike Mayberry says:

    If you check the link to the prior blogs, there are paper references at the bottom of the articles including different versions of the III-V stack. Yes looking forward, a III-V device with sufficient coupling should be better than a silicon trigate. We still need to verify how such a device scales. Still further out, stacking multiple carbon nanotubes with gate all around should be still better though that is well beyond our ability to fabricate today.