Transistors: Past, Present, Future, and Future-er

Today I had the privilege of presenting a plenary talk at the 2010 Device Research Conference (DRC) at Notre Dame University in South Bend, Indiana. DRC is one of the premier conferences in the semiconductor industry, and the focus is on what kinds of semiconductor devices will need to be researched now for them to be ready for production use in the future. The title of my talk was “Transistors: Past, Present, Future, and Future-er” (catchy, no?). I used my hour to talk about the state of transistors until the year 2000 (“Past”), from 2000 to 2010 (“Present”), from 2010 to 2020 (“Future”) and beyond 2020 (“Future-er” – yes, I know it’s not a word). Preparing for this talk was an eye-opening experience. I had to go back over the history of transistors from the early days of Robert Noyce and Gordon Moore to where we stand today to what my crystal ball says we’ll need in the distant future.

In 1965, Gordon Moore wrote a seminal paper in Electronics that the numbers of transistors on a chip would double every 18 months (later revised to every 24 months). Moore’s prediction, which everyone at Intel knows as Moore’s Law, proved to be amazingly prescient. The trend has continued to this day, 45 years after the paper. In reality, Moore’s Law is not a “Law” as engineers and scientists use the word. That is, it’s not some immutable law of nature. Rather, it serves as a self-fulfilling guide for the industry as to what rate of process development ought to be possible. The engineers at Intel and throughout the industry are the ones who make Moore’s Law a reality.

Up until about 2000, the “rules” for scaling were fairly well understood by all. Scale the gate oxide thickness; gate pitch, length and width; junction depths; and supply voltage, and the result is a trifecta of good news – cheaper (smaller) die, higher frequencies, and lower power. Sure, some innovations were needed along the way like halo implants and spacer-modulated tips, but the basic game plan was clear. All companies in the industry were able to do this, with varying but similar degrees of success.

Around the year 2000, things began the change. The main problem for everyone was that the gate oxide couldn’t scale anymore. The consequent gate leakage increase was causing too much power consumption. New and much more significant innovations were needed to keep pushing transistor performance. For Intel, these were strained silicon and high-k/metal-gate. Over the course of a decade, through 4 generations of strained silicon and 2 generations of high-k/metal-gate, Intel went from being at parity with the industry to having a significant lead. Intel has a >3 year lead in shipping high-k/metal gate products and a >1 year lead in shipping 32nm products (assuming our competition eventually ships HK/MG and 32nm products early next year). The key to building that leadership was making the right technical decisions at the right time.

Making the right technology choices at the right time is an inherent advantage Intel has because of our unique Research-Development-Manufacturing model. In our approach, Research and Development are tightly coupled through an intensive Pathfinding phase for each process program, wherein we make sure that new process options are (a) necessary to meet our technology goals and (b) ready to be integrated into a production-worthy process. This stands in stark contrast to many other semiconductor companies, where Research and Development are often silos of independent innovation and decision-making.

Looking to the Future, I expect this approach to continue serving us well. As we consider the technology options for the next decade, with many interesting ideas like Tunnel FETs, FinFETs, III-V and Ge-based devices, our tight coupling between the Research phase and Development phase will allow us to make the right choice at the right time. The future looks bright and, when the next round of innovations are needed to maintain our leadership, we look well placed to be ready for it!