Not all silicon processes are created equal.

There is a lot of talk right now about 45nm – the newest and most exciting step along the Moore’s Law story. (Yes, it IS exciting…)

Essentially it means that transistors can be made smaller, and the smallest feature size is only 45nm across, that is less than 200 silicon atoms wide.

Ok, so we have tiny transistors, this means we have space for more of them, and this means more capabilities built into the chips – these could take the form of more performance or other goodness such as virtualization or new instructions.

But Intel has been loud and proud recently about their 45nm transistors – and not just because we are first again. But because our new 45nm transistors are built using revolutionary new materials (a High K gate dielectric and new metal gates) that will allow for faster and lower power devices. So why should anyone care?

Gordon Moore (utterer of the famous law) expressed his excitement quite clearly:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

So the biggest change in 40 years! This is to transistors what breaking the sound barrier was to aviation– and does the rest of the industry care?

Well – several companies have been claiming their new 45nm transistors will be as good as Intel’s. When confronted with such assertions, several questions should be asked:

Do they have designs for both necessary types high-K/metal gate transistors, both PMOS and NMOS? Hint: you need the full complement to make a chip that will see the full benefits from the new materials; you can’t stick a jet engine on one wing and propeller on the other.)

Have they created any working chips using the new materials?

Will their chips be 100% lead free?

Will their 45nm chips contain high-K metal gate transistors?

Thanks to Intel’s new 45nm high-K metal gate transistors process we can pack 2,500 CPU dies onto a single 300mm wafer. These are our recently announced “Silverthorne” low power processors that benefit greatly from energy sipping silicon.

Because only Intel is bringing out truly revolutionary transistors this year, only Intel processors will benefit from the densest, fastest and lowest power mass-produced CPU transistors – and that means better high scores for gamers, better video playback for movie buffs, better server performance, and a longer lasting laptop battery.

See, transistors are now cooler. 🙂

2 thoughts on “Not all silicon processes are created equal.

  1. It would be nice if these transistors made their way into other devices. The x86 cellphone, x86 DVR, etc.
    If more devices were x86 then converging them would be a lot easier down the line. For example, I see no reason why LED and LCD televisions of the future are not as powerful as a quad core laptop w/ the the NAND/PRAM and microprocessors all located inside the television.
    Intel inside would take on a new meaning.

  2. Every thought is God Given. Let us utilize it for the benefit of humanity. This is how every invention has come and so this be.
    1.Reduce the cost of computer
    2.Reduce the energy consumption of the world for computing
    3.Simplify the design of a computer
    4.Increase Scalability of a computer
    5.Decrease complexity of fabrication.
    High performance Single Chip Computer.
    End User only needs:
    1.Computer at low cost
    2.Good / Acceptable performance for 90% of the applications that we use
    3.Enough space to keep data.
    The end user does not need to know ( or he bothers about ) what is the underlying technology that he see as a computer. He does not need to know
    whether the instruction set is RISC / CISC etc. He is only bothered about the overall response time and the available space to keep data.
    No Individual needs a space more than 4GB in the Flash for Software and another 4GB space for keeping data at runtime. Any one who is exceeding
    this already falls into the category of enterprise computer and not home / desktop computing.
    We designed the computer. We labelled the parts like CPU Memory HDD and so on.
    It is like physics, chemistry, biology……. but knowledge is one. One knowledge can be applied in the other for any circumstance to solve
    problems. There is nothing like this knowledge is from physics, this from chemistry etc.
    All knowledge and understanding is God Given to this mankind.
    The collection of all knowledge which can be applied by any individual is called common sense.
    So the definition of CPU, Memory, HDD have all originated from the properties of materials ( Material Science ).
    Ultimately it could be Permanent and temporary and their speeds.
    Technology has evolved. Now it is time to integrate all the pieces.
    The pieces by itself has no significance, but after integration, It makes a marvellous discovery a computer.
    Let us take CPU and Memory.
    One cannot exists without the other.
    =>Integrate CPU and memory. CPU manufacturers can make memory and Memory manufactures can make FFS ( Flash disk etc )
    We have un necessarily made a wall between the manufacturing of these components of a computer.
    Ultimately what we are trying to do is to enhance performance of a computer while keeping the cost low.
    But the real problem is we have split the components by function and then try to decrease the cost.
    Splitting by components increases the cost and integration decreases the total cost.
    For the end user, the total cost of the computer should be less. ( He does not even care whether there is a CPU or memory in reality and how much
    of it exists in what space.) [ Do we really need to know how many transistors / gates / flip flops really is required to do our computing ? ]-
    Definitely not.
    =>Integrate CPU and memory.
    Ultimately what we are trying to do is to enhance performance of a computer while keeping the cost low.
    In my observation in the last 20 years, what we are trying to solve is the speed of computing.
    This is achieved by Caching.
    1.By hardware / firmware at the CPU level.
    2.By hardware / Software at the memory level.
    3.By disk electronics Raid / San / Nas at the HDD level.
    Because of the above implementation methodology ( which was correct at the original time of invention of a computer )
    I/O ( Input / Output ) is CPU Intensive. ( Because it is logic oriented )
    And whenever there is a logic there is a problem in performance. ( This was the original reason why we put this piece of logic in
    Now, Still we have the performance Issue.
    Solution and New Design.
    Today, the CPU Speeds and Memory Speeds have become compatible.
    Ideally both the units should be operating at the same clock speed.
    IF required, the CPU speed can be reduced and memory speed can be increased so that there is no latency.
    So, CPU can operate ad 1GHz and Memory at 1GHz.
    =>Integrate Memory and CPU into one logical unit operating at same clock speed ( call it ICPU )
    1.This can be done as on die Memory OR
    2.Only for reducing further cost, ( and for easier fabrication ) this can reside outside the CPU die.
    ( Either 2 / 1 GB )
    1.All Cache logic TLB / L1,L2,L3 cache and all logic can be completely removed.
    2.No need to have memory controller ( Memory itself is at clock speed ).
    3.Ultra Reduced Parallel Instruction Set computing.
    I.Ultimately what a chip needs is
    A.Vector Registers 32 bit wide of min 2 sets length ( or depth ) 255
    B.Built in FP Vector Registers of min 2 sets length 255
    C.All the Standards Registers like IP Flags CS DS SP BP …..
    II.Vector Instruction Set ( Leading 8 bit operation Trailing 8 Bit Depth ) 16 bit instructions ( Tailing all zeros for non vector )
    A.Vector add sub mpy div cmp
    B.Read Vector (from memory )
    C.Write Vector ( to memory )
    E.CS cannot become DS / and memory management Flags for OS implementation.
    F.No other un needed instructions.
    4.No need to have multiple cores on a CPU ( We can add more ICPU for horizontal scalability )
    This Integrated CPU and Memory Module is called as ICPU ( say ) or as daughter card.
    This ICPU will perform 10 times faster than the current technology ( even though on paper it is operating at a lower speed ).
    [Note: Speed does not translate into performance. But the re-design of the ICPU will ]
    CPU is done by company A
    Memory by company B
    HDD by company C
    and so on….
    But each one is trying to reduce their own cost. ( But with the current implementation, the cost cannot be reduced )
    So we need to Integrate all the three technologies.
    By Integration, We will eliminate all the un needed HW / SW required to perform the same task ( basically caching ).
    Let us take the Home / Office Desktop or Laptops.
    In 99.99% of these machines
    CPU cannot be changed for life
    Mem cannot be changed for life ( because the technology is changing fast )
    Display is fixed
    Network Card is fixed
    KBD and other accessories are today Built in in mother board
    Practically, Once purchased, the machine cannot be upgraded for life.
    The Real change could only be done in the Hard Disk ( For its life is too short when comparing Solid State devices )
    Why we need flexibility? ( In reality this flexibility does not exist for the end user.)
    Standard Display adaptor and standard network card (10Mbps / 100Mbps ) DSP can be made on die.
    Integrate all into a Single Chip.
    Hence, High performance Single Chip computer is born.
    You only need a DMA controller ( or any other appropriate HW ) to access HDD for enterprise.
    A 32 bit LBA ( with block size 255 bytes ) is sufficient to handle up to a few Terra bytes sufficient for enterprise computing.
    For Enterprise computing with supercomputing power,
    We need to design a Hardware which can support multiple ICPU ( or daughter card ) for horizontal scalability.
    The only issue is how to handle IPC ( Inter process communication ) in the new proposed technology.
    I have taken the logical solution from the BARC designed Neural Network computer design.
    They were able to use industry standard computers and design Super computing power with 486 chip ( 10 years back )
    We can use the same model to build the next generation super computing – Enterprise computers.
    In Practice IPC Does not exists. ( It was designed for SMP Architecture )
    The only two major application is OS ( Operating System ) and RDBMS.
    In Both these application there is a well defined Transaction boundary during which there is no sharing.
    This is implemented in OS using Shared Mem and Semaphores ( to lock multiple access ).
    All RDBMS have to Write to disk after the completion of such a task during which no shared access is allowed.
    ( Access happens from the rollback segments ) and not online sharing.
    In either case, true IPC / Memory sharing need not exist ( in the way it is currently implemented )
    We can design and implement a new cache fusion technology for inter ICPU communication for further performance enhancement.
    Optionally we can read from disk.
    Multiple OS can be supported on a single hardware running on different ICPU for large enterprises ( Virtualization ).
    For Laptop / Desktop computing to be made completely Solid state,
    1.We Already have Flash File system ( For OS and Removable Storage )
    2.ICPU ( for memory and processing )
    3.RFS ( Ramdisk File system – A new invention to be made based on FFS but on conventional memory – for infinite writes – with battery backup )
    A.This RFS is used for runtime configuration which can be changed or optimised.
    B.This RFS can be used for storage for download and install and upgrade of existing software
    C.An Advanced Flash Utility which comes with the BIOS at boot time ( To upgrade a Software from RFS to FFS at boot time ) [ based on the
    principle of RDBMS – All or nothing => complete re-install of existing Software including OS upgrade. ]
    D.This will enable the evolution of the Software with time and protecting investment for future with less complexity.
    E.We will be complete out of Virus ( The Greatest nightmare of the industry )
    I have read the design specification of a quantum flip flop in 2000.
    The order of complexity of the control unit is defined by the order of factorial ( n-1) where n is the state of a flip flop.
    For a single flip flop of n states, the Order of complexity of the control unit is factorial ( n-1) to define its n’th state.
    Suppose there are million flip flops to be used in such a computer, a factorial is explosive and un imaginable.
    =>Quantum computing is not achievable.
    But High Performance Single Chip Computing is Achievable with scalability. Let us start working on this new design.
    We are in the making of Information Revolution.
    This can happen only with understanding and transformation.
    Scalability is sufficient if it is horizontal ( but not vertical or by speed ).
    We can definitely reduce cost by 10 times.
    Learn from cell phone industry.
    A single chip cell phone is costing under $10.
    We need to fix the cost and performance of the parent Industry ( Computers ).
    A single chip computer should only cost $100. This is achievable.
    To Fulfill the Vision of MIT ( One Laptop per child ),
    We need 6 Billion of the new machine.
    We need Lighter / Secure HW and efficient OS and application for the World which is completely Solid State.
    Thank you for your time.

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