WWT’s Advanced Technology Center provides access to seven diverse high-performance, FPGA-accelerated application demos

World Wide Technology (WWT) has developed an FPGA “Center of Excellence” within its immense Advanced Technology Center (ATC) to provide its customers with a one-stop resource for exploring the performance benefits of FPGA acceleration based on the Intel® Acceleration Stack for Intel Xeon® CPU with FPGAs. The ATC creates a collaborative ecosystem that enables customers and partners to collaborate and to design, construct, demonstrate, and deploy integrated architectural solutions based on a number of hardware and software technologies. The ATC includes three data centers with more than 300 racks of equipment that can be used to build solutions for big data, collaboration, computing and cloud, mobility, networking, security, and storage challenges.

WWT’s FPGA Center of Excellence within the ATC currently features demonstrations of seven market-ready FPGA solutions that integrate software applications and FPGA-accelerated hardware. The seven demonstrations include a broad range of applications and workloads from different vendors including:

 

  • rENIAC: A Cassandra-based NoSQL database management system based on a distributed data engine that’s designed to handle very large amounts of data.
  • Swarm64: An FPGA-accelerated, PostgreSQL relational database for enterprise data analytics that can handle queries as much as 50X faster than non-accelerated versions.
  • Falcon Computing: Genomic analysis using an FPGA-accelerated version of the Broad Institute’s Genome Analysis Toolkit (GATK) that delivers 15X the performance of the non-accelerated version.
  • CT-Accel: A high-performance, FPGA-accelerated image processor that encodes, decodes, resizes, and crops JPEG, WebP, and Lepton images with as much as a 4X performance improvement.
  • Megh Computing: FPGA-accelerated, real-time analytics on streaming big data that reduces latency by as much as 10X.
  • Levyx: FPGA-accelerated, low-latency, I/O-intensive Black Scholes financial modeling that reduces data latency by as much as 10X or more.
  • Napatech: High-speed network accelerators for a number of cybersecurity applications, with performance improvements currently ranging from 3X to 7X.

 

If you are interested in accessing the powerful FPGA-accelerated tools in WWT’s ACT, click here.

 

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Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.

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Published on Categories Acceleration, Cloud, PACTags , ,
Steven Leibson

About Steven Leibson

Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.