WWT’s Advanced Technology Center explains why Intel® FPGA PACs are often a superior choice for data center acceleration

The Advanced Technology Center at World Wide Technology (WWT), a technology solution provider and Intel® Partner Program member, actively tests and demonstrates data center applications ranging from accelerated analytics to database management, cybersecurity, and even supercomputing. Earlier this month, the company published a blog about WWT’s experiences with using Intel® FPGA Programmable Acceleration Cards (Intel® FPGA PACs) to accelerate data center workloads, improve workload performance, and free server CPU processing cycles so that they can be employed for revenue-generating workloads. Zach Splaingard, Earl Dodd, and Matthew Halcomb at WWT wrote this blog, which is titled “FPGAs Emerge as the Flexible Acceleration Choice.”

The WWT blog begins with a short case study:

“A mid-size manufacturer needed to add cybersecurity and network monitoring workloads to its general-purpose data center, creating a spike in demand for compute power. Deploying a mainstream network interface card would have resulted in critical (and costly) packet loss and degraded performance.

“The better solution: an… Intel FPGA PAC, customized for the cybersecurity workload at hand. Adding the PAC card relieved the server CPU of the heaviest compute tasks, freeing up processing resources for essential business applications and services.”

The blog then notes that several technologies from Intel and from members of the Intel Partner Program contribute to making it easier than ever to employ Intel® FPGAs in Intel FPGA PACs for data center workload acceleration:

“New Intel FGPA technologies offer fast deployment and standardization through Intel PACs and the Intel® Acceleration Stack. Independent solution vendors have pre-designed FPGA accelerator solutions that seamlessly integrate into shared libraries, software frameworks and custom software applications.”

The blog then summarizes the benefits gained by using Intel FPGA technology in the data center:

“In a ‘suitability matrix’ of accelerator choices, FPGAs are a stand out option, especially when measured against other accelerator options across a range of metrics, including relatively low price, performance per-watt per-volume, ruggedness, security, time to market, increased lifecycle and total cost of ownership (TCO). FPGAs are the only solution in which the hardware can be tailored repeatedly to fit the software exactly.

“In short, FPGAs win in spaces where the workflow is highly dynamic and flexible, where power consumption must be minimized, low latency is a priority or the accelerator must function independently from the CPU.”

Finally, the WWT blog discusses three different case studies for Intel FPGA PAC use in the data center:

  1. Edge to Core – When you need a flexible, hardened edge solution
  2. Supercomputing – Overcoming power and cooling demands
  3. In-store image recognition analytics

 
These case studies lead to a concise conclusion in the WWT blog:

“…WWT finds that FPGAs are often the superior choice over GPUs and ASICs for compute and data acceleration.”

For more information, be sure to read the WWT blog: FPGAs Emerge as the Flexible Acceleration Choice.

 

 

Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge.

 

 

Notices & Disclaimers

Intel does not control or audit third-party data.  You should consult other sources to evaluate accuracy.

Intel technologies may require enabled hardware, software or service activation.

No product or component can be absolutely secure.

Your costs and results may vary.

© Intel Corporation.  Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  Other names and brands may be claimed as the property of others.

Published on Categories Acceleration, Cloud, PACTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.