Want a preview of the Intel keynote at The Next FPGA Platform Event? The Next Platform just published one

Next week, The Next FPGA Platform event takes place in downtown San Jose. This day-long event includes several talks and panels devoted specifically to datacenter topics with an emphasis on FPGA acceleration. Several speakers and panelists from Intel will be there and Timothy Prickett Morgan, co-editor and co-founder of The Next Platform, has just published an article titled “Covering All The Compute Bases In A Heterogeneous Datacenter” that previews the event. In particular, he quotes Jose Alvarez, Senior Director in the CTO Office for the Programmable Solutions Group at Intel, who will be giving one of the keynotes at the event. Alvarez told The Next Platform:

“One architecture doesn’t fit everything, and there are a lot of different workloads. There are scalar, vector, matrix, and spatial architectures and those are very uniquely positioned to solve multiple problems. For scalar, you may use a CPU. For vector processing, you may use a GPU. For matrix, you may use a dedicated ASIC as we do for machine learning and artificial intelligence. And for spatial, you might use an FPGA.”

The article goes on to quote several other things that Alvarez told The Next Platform about various technologies and architectures that Intel is using to continue the company’s close, half-century-long alliance with Moore’s Law.

If you want to read what Alvarez told The Next Platform, then click over to Morgan’s article using the link above.

Better yet, plan on attending The Next FPGA Platform event in person on January 22 in San Jose. (See “FPGA Acceleration in the Datacenter: See and Hear High-Level Experts from Intel and FPGA Partners at The Next FPGA Platform Day-Long, Live Event – January 22 in San Jose” or click here for the event information page with a full agenda.)

Better yet, just click here to register for the event.

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.