VMware vSphere 6.7 now supports the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

According to this VMware blog published in January, VMware has expanded its array of supported hardware accelerators in its vSphere hypervisor to include support for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA). Why? The VMware blog explains:

“The highly parallel architecture of FPGAs allows for higher performance, lower latency, lower power consumption, and higher throughput for computations. Typical workloads for FPGA devices include Network Function Virtualization (NFV), deep neural networks, digital signal processing, and cryptography workloads.”

Intel PAC with Intel Arria 10 GX FPGA is a PCIe-based FPGA accelerator card for data centers that offers both inline and lookaside acceleration. It provides the performance and versatility of FPGA acceleration and is one of several Intel platforms supported by the Acceleration Stack for Intel® Xeon® CPU with FPGAs.

The VMware blog continues:

“To use the Intel® Arria® FPGA with VMware vSphere, version 6.7 Update 1 is required. DirectPath I/O is the only supported method today. This means that the hardware address of the PCIe device (the FPGA in this case) is directly exposed in the virtual machine.”

In addition to the VMware vSphere, version 6.7 Update 1, you’ll need the VMware SR-IOV (single root input/output virtualization) driver for the Intel Xeon CPU and the Intel PAC with Intel Arria 10 GX FPGA, which is for VMware Hypervisor version ESXi 6.7 U2. You’ll find that SR-IOV driver and an associated toolkit here in the Intel Download Center.

 

VMware is a member of the Intel® FPGA Partner Program.

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Published on Categories Acceleration, Arria, PACTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.