Two free Webinars to cover PCIe Gen4 and Intel® Agilex™ F-Series FPGAs in December

Intel® Agilex™ F-Series FPGAs and SoCs support PCIe Gen4 x16 operation at 16GT/s using a combination of hard and soft IP. Now you have two chances to learn about the architecture and key features of the Intel Agilex F-Series FPGAs’ PCIe Gen4 abilities including endpoint, root port, and transaction layer protocol (TLP) bypass modes; port bifurcation; autonomous hard IP (HIP) mode; and Single Root I/O Virtualization (SR-IOV) through a pair of Webinars.


  • The first Webinar takes place on December 3 at 9:00 AM Pacific Time: register here.
  • The first Webinar takes place on December 17 at 10:00 AM Central European Time: register here.


For more information about the Intel Agilex F-Series FPGAs’ PCIe Gen4 capabilities, see “Need PCIe Gen4 x16 version 1.0 capability with full PCI-SIG compliance in an FPGA today? Intel® Agilex™ FPGAs can deliver.”


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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.