Two free Webinars cover the myriad external memory-interface capabilities of the new Intel® Agilex™ FPGA and SoC families

Intel® Agilex™ FPGAs and SoCs give you more interface capabilities for external memories than ever before. Two new, free, 1-hour Webinars provide an overview of the extensive external-memory interfacing capabilities of Intel Agilex FPGA and SoC families and will show you how to integrate different external memory interfaces into your design, including ways to take advantage of resource sharing within the Intel Agilex devices to implement multiple interfaces.

The Webinar dates and times are:

 

  • January 16, 9:00 AM to 10:00 AM PT (Pacific Time)
  • January 21, 10:00 AM to 11:00 AM CET (Central European Time)

 

The Webinars will be conducted by Steven Strell, an Applications Engineer with the Intel Programmable Solutions Group.

 

  • Click here to register for the January 16 Webinar.
  • Click here to register for the January 21 Webinar.

 

For more information on Intel Agilex FPGAs and SoCs, see:

 

 

For more detailed technical information on the external memory interface capabilities of Intel Agilex FPGAs and SoCs, start here.

 

 

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Published on Categories AgilexTags
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.