Toyota sees 2x to 3x performance gains in PostgreSQL/PostGIS performance using FPGA-enabled servers and Swarm64 DA

In two benchmarks run by Toyota, Swarm64 DA (Database Accelerator) used in conjunction with a server containing an Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA boosted open-source PostgreSQL/PostGIS performance by a factor of 3x and delivered more predictable query performance (with 35x less latency variance) under concurrent loads. Swarm64 DA is an FPGA-accelerated, PostgreSQL relational database used for enterprise data analytics. When Swarm64 is installed, it programs the FPGA with hundreds of processes that work in parallel to write, read, filter, compress, and decompress data contained within database tables. This massive added parallelism lowers the CPUs’ workloads and increases their throughput. The overall result is much better server performance using fewer servers, which reduces overall TCO.

The results of these two PostgreSQL/PostGIS benchmarks are documented in a new White Paper titled “Measuring the impact of FPGA acceleration on PostGIS concurrent query performance at Toyota,” which is now available on the Swarm64 Web site. Tripling server performance means, for example, that a 5-node cluster of FPGA-equipped servers can handle the same PostgreSQL load as a 15-node cluster of servers equipped only with CPUs. This outcome has profound implications for capital equipment and operating costs in data centers. Put simply, FPGA-equipped servers with appropriate acceleration software can handle many more database workloads.

The benchmarks consisted of two scenarios:

Test Scenario 1: Obstacle detection. Find the list of vehicles that have been within 2 km of a random location within the last 6 minutes. The scenario assesses the efficiency of FPGA acceleration for the geospatial-optimized functions of PostGIS.

Test Scenario 2: Analytics scenario on the NYC Taxi Dataset, a 267 gigabyte table consisting of 1.1 billion rows of data. This data set is too large to be held in the servers’ RAM and therefore required SSD accesses.

In Test Scenario 1, the FPGA-equipped servers delivered more consistent query performance – with 35x less latency variance – and 3x faster performance over 3200 queries while scaling the number of concurrent users from 1 to 32. In Test Scenario 2, query response latency dropped by a factor of 2x to 3x using FPGA-accelerated servers, depending on the query.

To download a copy of the White Paper from Swarm64, click here.

Note: Swarm64 is a member of the Intel® FPGA Partner Program.

 

Legal Notices and Disclaimers:

 

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.

Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.

Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate.

Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings.

Circumstances will vary. Intel does not guarantee any costs or cost reduction.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

Altera is a trademark of Intel Corporation or its subsidiaries.

Cyclone is a trademark of Intel Corporation or its subsidiaries.

Other names and brands may be claimed as the property of others.

 

 

Published on Categories Acceleration, Arria, PartnersTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.