Last November at Supercomputing ’19 (SC19), the Gen-Z Consortium booth contained a proof-of-concept (POC) SQLite database acceleration demo that showed a 5x performance improvement in the average database INSERT operation time, with a clear path to even better performance. (See “Gen-Z Consortium demos 5x SQLite database acceleration at SC’19 with an Intel UPI link between an Intel® Xeon CPU and an Intel® FPGA.”) That demo was based on an Intel® Xeon® CPU communicating with an Intel® FPGA configured over a coherent, low-latency Intel® Ultra Path Interconnect (UPI) link using an Intel UPI Home Agent IP block contributed by Intel specifically for this POC demo. The UPI IP block was connected to a Gen-Z controller IP block, also instantiated in the FPGA, which ultimately communicated with a Gen-Z Memory Module (ZMM). The Gen-Z controller IP was developed and provided by Intelliprop (an Intel® FPGA Partner Program member). Last week, the online tech site The Next Platform discussed this demo in an article written by Timothy Prickett Morgan titled “Gen-Z Memory Servers Loom On The Horizon.” The relevant part of the article states:
“…the FPGA team at Intel worked with server makers HPE and Dell and chip designer IntelliProp to create a bridge from CPUs to remote Gen-Z ZMMs and compared the latency of a transaction processing benchmark on the SQLite database with the data being stored either on local NVM-Express drives on the server or on the remote Gen-Z memory. In this case, IntelliProp created a bridge from the [Intel] UltraPath Interconnect (UPI) NUMA links used on [Intel] ‘Skylake’ and ‘Cascade Lake’ processors to the Gen-Z protocol… The latency of database reads was 5X lower across the Gen-Z link to the ZMM than it was for locally attached NVM-Express drives.”
Moving forward, this POC demo and the associated IP will migrate to the recently announced Intel® Stratix® 10 DX FPGA, which supports the Intel UPI protocol as well as PCIe Gen4 x16 with hardened IP. (See “Talk to PCIe Gen4 x16, Intel® UPI, Intel® Optane™ DC Persistent Memory, and SDRAM with one Intel® Stratix® 10 DX FPGA.”) Meanwhile, Intel and other industry leaders including Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, and Microsoft are developing a next-generation, coherent CPU interconnect called the Compute Express Link (CXL), which will be supported by the new Intel® Agilex™ FPGA family. (See “How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?”)
If you are struggling to connect some of these coherent dots, The Next Platform will be holding a live event next week in San Jose on January 22 called The Next FPGA Platform. This event gathers together many preeminent industry leaders to bring you up-to-the-minute information about and deep, expert insights into FPGAs and FPGA acceleration in servers and datacenters. Intel is a Platinum sponsor for this event. Timothy Prickett Morgan, co-editor and co-founder of The Next Platform and author of the article discussed above, is one of the event’s hosts. For more information about The Next FPGA Platform event, see “FPGA Acceleration in the Datacenter: See and Hear High-Level Experts from Intel and FPGA Partners at The Next FPGA Platform Day-Long, Live Event – January 22 in San Jose” or click here for the event information page with a full agenda. Or, just click here to go ahead and register.
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