Terasic DE10-Agilex Accelerator PCIe board combines Intel® Agilex™ F-Series FPGA with four DDR4 SO-DIMM SDRAM sockets and two QSFP-DD connectors

If you’re itching to get your hands on the innovative features built into the new family of Intel® Agilex™ FPGAs like the second-generation Intel® HyperFlex™ architecture or the improved DSP capabilities including half-precision floating point (FP16) and BFLOAT 16 computational abilities, then consider the new Terasic DE10-Agilex Accelerator board. This PCIe card combines an Intel Agilex F-Series FPGA with four independent DDR4 SO-DIMM SDRAM sockets and two QSFP-DD connectors on a three-quarter length PCIe board.

The board’s host interface is a PCIe Gen 4.0 x16 port. Each SO-DIMM memory socket accommodates 8 or 16 Gbytes of DDR4 memory, for a maximum total SDRAM capacity of 64 Gbytes, and each QSFP-DD connector accommodates Ethernet transceiver modules to 200G. The board is available with two different cooling options: a 2-slot version with integrated fans or a single-slot, passively cooled version.

 

The Terasic DE10-Agilex Accelerator PCIe card combines an Intel® Agilex™ F-Series FPGA with four independent DDR4 SO-DIMM SDRAM sockets and two QSFP-DD connectors

 

The Terasic DE10-Agilex PCIe board supports the Intel® OpenVINO™ toolkit, OpenCL™ BSP, and Intel® oneAPI Toolkits used for developing code for myriad high-performance workloads including computer vision and deep learning. The Intel Agilex FPGA family delivers up to 40% higher performance1 or up to 40% lower power1 for data center, NFV and networking, and edge compute applications.

For more technical information about the Terasic DE10-Agilex Accelerator Board or to order the product, please contact Terasic directly.

 

Notices and Disclaimers

1 This comparison based on Intel® Agilex™ FPGA and SoC family vs. Intel® Stratix® 10 FPGA using simulation results and is subject to change.

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Published on Categories Acceleration, Agilex, AI/ML, OpenVINO, VisionTags , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.