Tag: Stratix

• rENIAC Data Engine and Intel® Programmable Acceleration Card boost Cassandra database performance in VMware vSphere virtual environment Apache Cassandra – the free and open-source, distributed, wide column store, NoSQL database management system (DBMS) designed to handle large amounts of data across many commodity servers – provides high availability with no single failure point. This DBMS offers robust support for clusters spanning multiple datacenters, with asynchronous master-less replication allowing low-latency operations for all clients. FPGAs, which have been...
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• Intel has just announced its first AI-optimized FPGA – the Intel® Stratix® 10 NX FPGA – to address the rapid increase in AI model complexity FPGAs have been used in the area of hardware customization for decades. The hardware customization capability taps into the value proposition of FPGAs such as pipelining for applications that require low batch size and low latency, and flexible fabric and I/O functions to scale up and deliver entire systems. Intel’s silicon and software portfolio, which includes FPGAs, empowers our customers’...
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• Semiconductor Engineering Magazine wonders whether Chiplet Technology is Good or Bad. Intel’s answer: Good, Very Good Mark LaPedus, the Executive Editor for Manufacturing at SemiEngineering.com, recently published an article titled “The Good And Bad Of Chiplets.” From the Intel perspective, there’s only good. LaPedus writes: “With chiplets, the goal is to reduce product development times and costs by integrating pre-developed dies in an IC package. So a chipmaker may have a menu of modular dies, or...
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• Accelerating Memory Bound AI Inference Workloads with Intel® Stratix® 10 MX Devices Artificial intelligence (AI) systems are increasingly constrained by memory solutions that overly constrict available memory bandwidth. For example, Recurrent Neural Networks (RNNs) used in AI applications such as finance, genome mapping, and speech AI – including Automatic Speech Recognition (ASR), Natural Language Processing/Understanding (NLP/NLU) – have two common traits: They are memory intensive They require very low latency Consequently, RNN...
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• Ayar Labs and Intel demo FPGA with optical transceivers in DARPA PIPES project: 2 Tbps now, >100 Tbps is the goal The US Defense Advanced Research Projects Agency (DARPA), has announced that researchers from Intel and Ayar Labs have demonstrated early progress towards improving chip connectivity using photonic interconnect under DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program, which is exploring ways to expand the use of optical components to address the performance, efficiency, and distance constraints of copper...
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• How Heterogeneous Device Design and Manufacturing Leads to Success   By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel The following guest blog is based on remarks by Patrick Dorsey during a panel discussion on “FPGA Hardware Innovations” at the recent The Next FPGA Platform event, held in San Jose, California on January 22, 2020.   One of the looming challenges for FPGA hardware design is...
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• The Three Levels of Heterogeneity: Devices, Systems, and Software By Jose Alvarez, Senior Director, Intel CTO Office, PSG   The following blog is adapted from a keynote speech that Jose Alvarez presented as the recent The Next FPGA Platform event, held in San Jose, California.   There are three levels of heterogeneous integration. It’s a simple taxonomy. First, there’s heterogeneous integration at the chip level – the device level....
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• The Next Platform discusses Gen-Z coherent memory, UPI, and FPGAs for server architecture acceleration Last November at Supercomputing ’19 (SC19), the Gen-Z Consortium booth contained a proof-of-concept (POC) SQLite database acceleration demo that showed a 5x performance improvement in the average database INSERT operation time, with a clear path to even better performance. (See “Gen-Z Consortium demos 5x SQLite database acceleration at SC'19 with an Intel UPI link between an Intel® Xeon CPU and...
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• Be sure to read EEJournal’s new article about the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M FPGA with 10.2 million LEs Last month saw the announcement of the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M FPGA with 10.2 million LEs (logic elements). (See “Intel announces Intel® Stratix® 10 GX 10M FPGA, world’s highest capacity with 10.2 million logic elements. Targets ASIC Prototyping and Emulation Markets.”) This device shipped to customers prior to the announcement and two leading vendors...
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• S2C’s free, 2-hour ASIC prototyping Webinar on December 10 will show you how to prototype billion-gate designs on world’s highest capacity FPGA Last month saw the introduction of the Intel® Stratix® 10 GX 10M FPGA, the world’s highest capacity FPGA. This device specifically targets ASIC emulation and prototyping applications. Within days, S2C, a Gold member of the Intel® FPGA Design Solutions Network, announced that it was shipping a modular ASIC prototyping system based on this FPGA, the S10 10M Prodigy Logic System...
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