Silicom plans to use Intel® Agilex™ FPGAs to build smartNICs for datacenters and 5G applications

Silicom has big plans for the initial shipments of Intel® Agilex™ FPGAs that it is receiving through the Intel early access program. The company plans to develop a high-end smartNIC (smart network interface card) using the FPGAs to complement its existing smartNIC Server Adapters based on Intel Arria® 10 FPGAs and Intel Stratix® 10 FPGAs. Combining these smartNICs based on three Intel FPGA families will create a broad and formidable offering with a wide range of capabilities.


Figure 1. This Silicom FB2CG@S10GX2100 SmartNIC is based on an Intel Stratix 10 FPGA and features dual QSFP28 Ethernet ports with a PCIe Gen3 x16 host interface.


SmartNICs add high-speed networking capabilities to servers with the added benefit of being able to offload network-related tasks from the server CPU, which frees CPU cycles for more important, revenue-generating tasks. An example of such a task is IP security (IPsec) based on the pervasive SSL (secure sockets layer) standard protocol. Although several FPGA-based implementations exist, Silicom plans to become a leader in high-speed, FPGA-based SSL implementations using Intel FPGAs as the implementation vehicle.

Henrik Lilja, President of Silicom Denmark, notes a general need for acceleration in datacenters. He also sees considerable competition for this business, especially with the onset of high-demand networking associated with 5G communications, which is now starting to ramp. Lilja expects that the 5G market will really take off next year, in 2020. It’s this market that Lilja and Silicom are targeting with its smartNICs, including the one to be based on an Intel Agilex FPGA.

Lilja’s plans for using the Intel Agilex FPGA and participation in the Intel Early Access Program underscore his eagerness to ride the 5G wave with the most competitive smartNIC offerings he can conjure. Because of the nascent character of 5G technologies, Lilja believes that reprogrammable FPGAs will be essential for implementing and accelerating the most demanding 5G algorithms for several years, until the algorithms become firmly established and are ultimately set in stone. Only then can ASICs be used to implement these hardware algorithms.

Lilja points to 5G fronthaul as an example of such an application. The optimal distribution of processing tasks and the connection between baseband units (BBUs) and the remote radio heads (RRUs) for 5G fronthaul deployments is still being debated, even while early 5G networks are already being deployed. The situation is still very much in flux. However, the industry seems to be converging on at least two solutions, said Lilja, and while there is debate and uncertainty, FPGA programmability and flexibility represent significant competitive advantages in this market.

Lilja says that this 5G application also plays to one of Intel’s strengths – Lilja calls it “full support” – ranging from silicon to the software, IP, reference designs, and application help needed to bring new products to market quickly. Specifically, he cites the Intel FlexRAN reference design, which is an end-to-end Intel reference architecture for implementing software-based radio stations that can sit on any part of the wireless network from edge to core. “I would almost call [FlexRAN] a deployable solution for 5G fronthaul,” said Lilja, “All of this gives me great confidence in FPGA technology for years to come in datacenters.”


For an overview of documents related to the Intel FlexRAN architecture in the Intel Developer Zone, click here.


For more information about the Intel Agilex FPGA family and early recipients of these devices, see “Intel Driving Data-Centric World with New 10nm Intel Agilex FPGA Family” and  “First Shipments of 10nm Intel® Agilex™ FPGAs reach early access customers.”

Published on Categories 5G, Acceleration, Agilex, Arria, Cloud, Communications, Networking, StratixTags , , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.