Semiconductor Engineering Magazine wonders whether Chiplet Technology is Good or Bad. Intel’s answer: Good, Very Good

Mark LaPedus, the Executive Editor for Manufacturing at SemiEngineering.com, recently published an article titled “The Good And Bad Of Chiplets.” From the Intel perspective, there’s only good. LaPedus writes:

“With chiplets, the goal is to reduce product development times and costs by integrating pre-developed dies in an IC package. So a chipmaker may have a menu of modular dies, or chiplets, in a library. Chiplets could have different functions at various [manufacturing process] nodes.”

LaPedus’ article quotes Ramune Nagisetty, Director of Process and Product Integration at Intel, who discussed the use of chiplet technology at Intel:

“We’re in the early stages. More and more products from Intel and our competitors are going to reflect this approach moving forward. Every major foundry has a technology roadmap of increasing the interconnect densities for both the 2.5D and 3D integration approaches. In the coming years, we will see it expand in 2.5D and 3D types of implementations. We will see it expand into logic and memory stacking and logic and logic stacking.”

As LaPedus notes in his article, “Intel and a few others have the technologies in place to develop these products.”

In fact, Intel® FPGAs have incorporated chiplet technology for years. All members of the Intel® Stratix® 10 GX, SX, TX, and MX FPGA and SoC FPGA families and Intel® Agilex™ FPGA devices use chiplet technology to pair FPGA logic die with I/O tiles. (“Tile” is the name Intel uses for “chiplet.”) These I/O tiles connect to the FPGA die using a chiplet-to-chiplet (or die-to-die) interconnect standard developed by Intel called the Advanced Interface Bus (AIB) and Intel Embedded Multi-die Interconnect Bridge (EMIB) technology, which are both used for heterogeneous semiconductor manufacturing.

(Note: Early last year, Intel made use of the AIB standard royalty-free to enable a broad ecosystem of chiplets, design methodologies, service providers, foundries, packaging, and system vendors. DARPA has adopted the AIB standard for its Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program. For details, see “Intel releases royalty-free, high-performance AIB interconnect standard to spur industry’s chiplet adoption and grow the ecosystem.”)

In addition to using chiplet manufacturing technology for the I/O functions, the Intel Stratix 10 MX FPGA family uses chiplet manufacturing and packaging technologies to attach high-speed, 3D HBM2 DRAM die stacks to the FPGA fabric die within the FPGA device package, placing several gigabytes of fast memory very close to the FPGA logic. Here, chiplet technology facilitates quick access to data stored in the adjacent HBM2 DRAM stacks.

As LaPedus writes, “This is where chiplets fit in. A bigger chip can be broken into smaller pieces and mixed and matched as needed.”

LaPedus’ article in Semiconductor Engineering also explains another fundamental reason for the move towards chiplet technology:

“…no one technology can meet all needs.”

For example, the multiple memory die in an HBM2 die stack are manufactured using a memory-optimized manufacturing process. Memory processes require fewer metal layers than the advanced CMOS processes used for making FPGAs, which reduces the manufacturing cost for the memory.

Similarly, I/O functions that must drive long copper traces on circuit boards have functional requirements that diverge from the capabilities of the densest, fastest CMOS logic process available. Here again, the use of chiplet technology makes tremendous sense. Chiplet technology allows the appropriate pairing of function with semiconductor process technology on a case-by-case basis.

Rapid product development is yet another important reason for using chiplet technology. The use of tiles (or chiplets) give Intel the ability to reuse proven I/O silicon, which accelerates the product development process by eliminating the need to reimplement, retest, and validate functions that have already been tested and proven in silicon. For example, Intel Agilex devices utilize some of the same I/O tiles developed for and used to manufacture Intel Stratix 10 FPGAs.

Intel continues to develop new tiles and to introduce new devices based on these new and existing tiles. Because it’s much easier to design, fabricate, and test a tile rather than an entire FPGA, AIB and tile technology give Intel an express lane for bringing more new products to market faster.

 

Note: For more information, see “Chiplets (tiles) create a high-speed path for getting new FPGAs to market.”

 

You might also be interested in the Intel White Paper titled “Enabling Next-Generation Platforms Using Intel’s 3D System-in-Package Technology.”

 

 

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Published on Categories Agilex, EMIB, Stratix, TilesTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.