S2C launches Prodigy Logic Systems for prototyping large ASIC designs based on the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M

S2C has announced its new line of high-capacity S10 10M Prodigy Logic Systems for ASIC prototyping, based on Intel® Stratix® 10 GX 10M FPGAs. Members of this new ASIC prototyping system family include single-, dual-, and quad-FPGA configurations. A single-FPGA system supports ASIC designs as large as 80 million ASIC gates. S2C is currently shipping the single-FPGA S10 10M Prodigy logic system.

 

S2C’s single-FPGA S10 10M Prodigy logic system, based on an Intel Stratix 10 GX 10M FPGA, supports ASIC designs as large as 80 million ASIC gates.

 

“Intel’s Stratix 10 GX 10M FPGA is approximately 2.5 times larger than the current largest commercially available FPGA and is likely to be the highest-capacity single FPGA for the next 2 to 3 years. Using the Stratix 10 GX 10M FPGA will significantly increase current SoC/ASIC design prototyping capacity, simplify the prototyping process and achieve a much lower cost per gate,” commented Toshio Nakama, CEO of S2C.

The S2C S10 10M Prodigy Logic System is part of the company’s large, established Prodigy one-stop prototyping solution family, which works seamlessly with the company’s Prodigy Player Pro software; the Prodigy MDM multi-FPGA debug module that can run deep-trace debugging on multiple FPGAs simultaneously; and the Prodigy ProtoBridge to accelerate prototyping verification and software development.

 

For more information about the Intel® Stratix® 10 GX 10M FPGA, see “Intel announces Intel® Stratix® 10 GX 10M FPGA, world’s highest capacity with 10.2 million logic elements. Targets ASIC Prototyping and Emulation Markets,” and “Want to see a photo of the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M? How about two photos?

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.