Please join Intel for the oneAPI Developer Summit on April 26, 2021. It’s free!

Join Intel for the oneAPI DevSummit, part of the International Workshop on OpenCL (IWOCL) and focused on using Intel® oneAPI and Data Parallel C++ (DPC++) for accelerated computing across xPU architectures including CPUs, GPUs, FPGAs, and other accelerators. During this one-day LIVE virtual conference, you will learn from leading industry and academia speakers who are working on innovative solutions involving cross-platform, multi-vendor architectures.

If you’re working with FPGAs, there are two presentations of special note for you during the Developer Summit:

 

Comparative Analysis of Intel HLS Design Tools on a Case Study in Neuromorphic​:

Neuromorphic object-classification algorithms have lower memory and compute complexities than CNNs at similar accuracies, which can improve the scalability of ML apps. This presentation explores the efficacy of HLS design tools, including Intel® SDK For OpenCL™ Applications for FPGAs and Intel oneAPI DPC++ for Intel® FPGAs, in terms of design latency and hardware resources. The talk includes case study details featuring a novel, neuromorphic ML algorithm.

 

It’s Acceleration but Faster! A Business Perspective on FPGA Development:

This talk explores the balance between time-to-market and performance optimization of application development using FPGAs. Informed by Intel partner for Creative Solutions Space Ltd’s journey from RTL to OpenCL to Intel’s OneAPI platform, the discussion focusses on real world examples and the advantages of using agile approaches to FPGA development.

 

Interested? Want to attend this free Developer Summit? Then register here.

 

Need more info? Click here.

 

For more information about Intel DPC++, see “Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!

 

 

 

Notices and Disclaimers

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.