Intel developed EMIB (Embedded Multi-die Interconnect Bridge) technology, a foundational packaging technology used in the manufacture of all Intel® Stratix® 10 GX, SX, TX, and MX FPGAs and Intel® Agilex™ FPGAs, to enable heterogeneous integration of multiple semiconductor die in one package. This high-speed interconnect technology has proven essential to the rapid development and proliferation of the latest Intel® FPGAs. All members of the Intel Stratix 10 FPGA and SOC FPGA families employ EMIB technology for the heterogeneous integration of FPGA die with I/O chiplets (which Intel calls “tiles”) and high-density HBM2 DRAM stacks, which are used in Intel® Stratix 10 MX devices. The recently announced Intel® Agilex™ FPGA and SOC families similarly leverage EMIB, tile, and memory-stack technologies. (See “Intel Driving Data-Centric World with New 10nm Intel Agilex FPGA Family” for more information.)
Tiny Intel EMIB chips provide a high-performance way to interconnect two or more semiconductor die at far higher data rates than is possible with conventional multi-chip modules and are more cost-effective when compared to silicon interposers, a different 2.5D packaging technology. Silicon interposers employ TSVs (through-silicon vias) and a silicon interposer must be at least as large as all the interconnected die in the package, combined, making them very large pieces of silicon indeed. TSVs and the need for large silicon interposer chips both increase the packaging costs associated with 2.5D packaging technology relative to Intel EMIB technology.
Recently announced Intel devices that make use of EMIB technology include:
- The Intel Stratix 10 GX 10M FPGA – The world’s highest capacity FPGA (see “Intel announces Intel® Stratix® 10 GX 10M FPGA, world’s highest capacity with 10.2 million logic elements. Targets ASIC prototyping and emulation markets.”)
- The Intel Stratix 10 MX FPGA – The only available FPGA that combines high-speed HBM DRAM and 56 Gbps PAM4 SerDes transceivers in one package
- The Intel Ponte Vecchio general-purpose GPU, unveiled at last month’s Supercomputing 2019 conference held in Denver, Colorado
Intel EMIB chips are truly tiny, as shown in a photo that appeared as part of a recent Intel News Byte titled “Tiny Intel EMIB Helps Chips ‘Talk’ with Each Other.”
An Intel EMIB chip is not much larger than a single grain of Basmati rice. Photo credit: Walden Kirsch/Intel Corporation
One important thing to note is that the term “EMIB” applies specifically to the 2.5D interconnect and packaging technology, but not to the electrical I/O protocol carried by the EMIB chip. Intel Stratix 10 FPGAs have employed the AIB (Advanced Interface Bus) physical-layer protocol to interconnect FPGA die with I/O tiles and Intel released the AIB physical-layer protocol as a royalty-free chiplet interconnect specification earlier this year. (See “Intel releases royalty-free, high-performance AIB interconnect standard to spur industry’s chiplet adoption and grow the ecosystem.”) However, Intel EMIB interconnect technology is not synonymous with the AIB protocol. Intel EMIB chips can support other physical-layer I/O protocols as well.
For example, Intel Stratix 10 MX FPGAs incorporate one or two HBM2 DRAM stacks, which are connected to hard HBM2 memory controllers on the FPGA die by EMIB chips carrying as many as eight independent, 128-bit HBM2 Channels (configured as dual 64-bit Pseudo Channels) to each HBM2 memory stack. (See the “High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide” for more details.)
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