Open vSwitch for NFVi based on Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 achieves first-packet learning rate of 500K rules/sec, near-wireline performance

As the numbers of subscribers, competitors, and technology advances grow, communications service providers (CoSPs) need to differentiate their products and services while keeping improved power efficiency and the need to control total cost of ownership (TCO) as ever-present goals. Intel and HCL have addressed these challenges with a joint solution that combines Intel® hardware and HCL software. HCL has created a solution using the Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 that can dramatically increase network functions virtualization infrastructure (NFVi) routing and switching performance while preserving flexibility.

The resulting solution, the Open vSwitch (OvS), is a production quality, multilayer virtual switch that can implement software-defined networking (SDN), which is crucial to creating a closed-loop, fully automated NFVi solution. The OvS can either forward packets through a kernel-based datapath or by using the Linux Data Plane Development Kit (DPDK).

Aggressive software optimization offloads NFVi forwarding tasks to the Intel FPGA PAC N3000, yielding the following preliminary results1:

 

 

For more details, see the new Solution Brief titled “Increase NFVi Performance and Flexibility.” (Click on the link to download the Solution Brief.)

 

 

Notices and Disclaimers

 

1 Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intc.com.

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Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings.

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.