Nuvation’s Angry Moose offline game relies on a Cyclone® V SOC to launch a small stuffed moose at a wall of beer cans

Nuvation Engineering, a Gold member of the Intel® FPGA Design Solutions Network, was clearly thinking out of the box (or out of the six pack) when it developed an offline, Canadian-flavored, mechatronic riff on the Angry Birds mobile gaming app. The Nuvation game is called Angry Moose and it consists of a 3D-printed slingshot that launches a small stuffed moose at a target built from a wall of what appears to be 26 stacked Moosehead beer cans (although I’m no expert on Canadian beer logos). Originally developed in 2013, Nuvation’s Angry Moose game started out as a project based on what was then an Altera® Cyclone® III FPGA. However, over the years, the project graduated to a Cyclone® V FPGA with an integrated NIOS II soft-core processor and ultimately to an Arrow Electronics SoCkit development kit based on a Cyclone® V SOC with a hardened, dual-core Arm processor core. The progression of Cyclone® FPGAs used throughout the game’s continuous evolution demonstrates the smooth continuity in both Intel® FPGA silicon and FPGA development tools. This continuity makes it easy to migrate and improve your designs over time and across multiple device generations – sometimes while having way too much fun.

This project also demonstrates one of the many uses for FPGAs: real-time, multi-axis motor control. The game uses memory-mapped PWM drivers instantiated in the FPGAs to control three linear actuators, which set the slingshot’s azimuth, angle, and stretch. These three actuators aim the moose at the beer cans and set the launch energy. The 3D-printed slingshot, the moose, and the wall-of-beer-cans target appear in the images below.

 

 

Three linear actuators controlling a 3D-printed slingshot, a stuffed moose, and a wall of beer can targets comprise Nuvation’s Angry Moose game. Photo credit: Nuvation Engineering

 

For more details about this project and its years-long development, see Nuvation’s blog titled “Cyclone V SOC FPGA Design: Lessons Learned.”

 

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The image at the top of this blog is not a moose. It’s an elk. He’s not angry either.

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.