New White Paper describes high-performance Next-Generation Core Networks Proof of Concept with FPGA-based NFV acceleration

Intel, Affirmed Networks, and Dell EMC describe a proof of concept for high-performance Next-Generation Core Networks (NGCN) in a new White Paper titled “Enabling Communications Service Providers to Meet 5G High Density I/O Goals through Software Optimization and Hardware Acceleration.” This White Paper describes a state-of-the-art solution for a commercial, standalone 5G core network (5GCN) that delivers 100 Gbps/CPU socket (200 Gbps in the next-gen solution) using a 100 GbE NIC and a Dell EMC PowerEdge R470 Server powered by Intel® Xeon® Scalable CPUs. FPGA acceleration supplied by an Intel® FPGA Programmable Accelerator Card (PAC) N3000 addresses I/O limitations, allowing termination of 100 GbE interfaces per CPU socket. Smart load balancing using Intel FPGA and CPU cache optimizations with Affirmed Networks’ revolutionary 5G User Plane Function (UPF) boosts software performance for 5GCN applications. This combination of software optimization and hardware acceleration delivers 20 Gbps/pCore, which is a phenomenal achievement.

NFV has emerged as a way of achieving the necessary resource flexibility, high utilization, and high levels of programmability needed to handle diverse 5G workload profiles. NFV is built on best-in-class IA infrastructure to provide optimal and cost-effective deployment. Intel FPGAs deployed in Intel® FPGA PAC N3000 cards as COTS accelerators serve as additional programmable elements for NFV workloads. These FPGAs further increase performance in NFV applications while saving energy, reducing costs, and preserving form factors.

PACs such as the Intel FPGA PAC N3000 are a quick and convenient way of adding FPGA-based processing capabilities to 5G servers. FPGAs allow these systems to handle high data rates on a single server and provide fine-grained and diverse quality of service (QoS) characteristics across multiple network slices in 5G network deployments.

The benefits of using the Intel PACs as a hardware accelerator for communications networks include:


  • Efficient scaling
  • Increased throughput capacity
  • Fast time to market
  • Flexibility
  • Lower TCO


Demand in 5G networks shift and change over time, so Intel FPGAs can be quickly reprogrammed to optimally address the new requirements while helping to lower both CapEx and OpEx for these systems. There are myriad high-performance NFV workloads that can benefit from these FPGA-based benefits including:


  • Hierarchical quality of service (H-QoS)
  • Traffic shaping
  • Virtual private networks (VPNs)
  • Firewalls
  • Deep packet inspection
  • Encapsulation/decapsulation
  • Virtual broadband networking gateways (vBNG)
  • Virtualized evolved packet core networks (vEPC/5GCN)
  • Internet protocol security (IPSec)


For more in-depth information and technical details about this NCGN proof of concept, please download the White Paper. Click here.



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Published on Categories 5G, Acceleration, PACTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.