New Video Demonstrates 116 Gbps PAM4 Transceiver Test Chip for Intel® Agilex™ I-Series FPGAs

A new Intel video shows the latest performance results for a high-speed, long-reach (LR) transceiver test chip operating at 116 Gbps with PAM4 modulation. The transceiver test chip, which is built with Intel 10 nm process technology, complies with the highest data rates of the CEI-112G-LR-PAM4 specification. The test chip’s 116 Gbps operation demonstrates the high-speed transceiver design’s added margin for existing 100/200/400 Gigabit Ethernet (GbE) standards and its ability to support emerging protocols and forward error-correction (FEC) standards.

The video also shows the transceiver chip’s transmitter sending a 116 Gbps PRBS31 data pattern to a receiver on the same chip through interconnect and external cabling representing a total insertion loss of greater than 35 dB from BGA ball to BGA ball on the chip. In this test, the transceiver chip’s performance exceeds the CEI-112G-LR-PAM4 specification’s raw bit error ratio (BER) requirement by almost three orders of magnitude even at 116 Gbps, Here’s a screen shot showing the de-embedded PAM4 eye diagram of the transceiver chip’s transmitter operating at 116 Gbps measured with an oscilloscope.

 

Measured PAM4 Eye Diagram with de-embedding of the I/O Transceiver Chip’s transmitter operating at 116 Gbps

 

The high-speed, long-reach, digital ADC and DAC based transceiver architecture used for this chip along with a hardened 100/200/400 GbE protocol stack will be incorporated into Intel® Agilex™ I-Series FPGAs, which are optimized for high-speed, bandwidth-intensive networking in Cloud, Enterprise, and Edge applications.

Here’s the 116 Gbps PAM4 Transceiver I/O Chip video:

 

 

For more information about this 116G LR PAM4 transceiver demonstration or to learn more about Intel Agilex FPGAs, please contact your local Intel salesperson.

 

 

 

Notices and Disclaimers

Transceiver TX compliance testing in accordance to Optical Interconnect Forum OIF CEI-112G-LR-PAM4 on Tuesday 3rd March 2020 at 106.25 Gbps, 112 Gbps, and 116 Gbps. Equipment used: Keysight DCA-X Series Wide-Band Oscilloscope N1000A, 85 GHz bandwidth. Intel EV Transceiver Platform, Aim-TTi TGF4162 Dual Channel Arbitrary Function Generator, Agilent E3631A DC Triple Output Power Supply.

Transceiver channel demonstration tested in accordance to OIF CEI-112G-LR-PAM4 specification on Tuesday 3rd March 2020 at 116 Gbps data rate, ysung PRBS31 data pattern >35 dB insertion loss. Equipment used: Intel EV Transceiver Test Chip Platform, Intel QUISI Panel 1A (ISI Channel Board), Aim-TTi TGF4162 Dual Channel Arbitrary Function Generator, Agilent E3631A DC Triple Output Power Supply. 1 m Rosenberger RF cables (x2), 0.3 m Rosenberger RF cables (x2), 67 GHz DC blocks. Ardent Concepts Terminate-R Multicoax assembly plus 6 inch tails (x4).

Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.

Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks.

Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available ​updates. See backup for configuration details. No product or component can be absolutely secure.

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Published on Categories Agilex, Communications, NetworkingTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.