Multi-rail power sequencer based on Intel® Max® 10 FPGA handles power-supply sequencing needs of CPUs, FPGAs, ASICs, and more

Sequencing regulated power to large ICs such as CPUs, FPGAs, and ASICs is a critical job that’s become increasingly complex as the number of power rails increases. The wrong power-up sequence can prevent a system from initializing properly and the wrong power-down sequence can cause data loss. If you’re facing a design with complex power-sequencing requirements, then the configurable Multi-Rail Power Sequencer and Monitor Reference Design based on an Intel® Max® 10 FPGA might be just the design solution you need. The Multi-Rail Power Sequencer and Monitor can simultaneously monitor and correctly sequence as many as 143 power rails by monitoring a combination of “power OK” (POK) digital signals and as many as 18 analog supply voltages, which should be more than adequate for just about any system design. The Multi-Rail Power Sequencer and Monitor also supports the PMBus 1.3.1 protocol, which is based on the I2C physical interface and used by many power-converter ICs and modules including many Intel® Enpirion® dc-dc stepdown converters. This power sequencer is a block-based reference design, as shown below, and you can remove any IP blocks that aren’t needed for your system design.

 

 

This reference design is fully described in a 41-page application note titled AN 896: Multi-Rail Power Sequencer and Monitor Reference Design.

You can download the Multi-Rail Power Sequencer and Monitor Reference Design here.

 

 

 

 

Legal Notices and Disclaimers:

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.

Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.

Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate.

Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

Other names and brands may be claimed as the property of others.

Published on Categories Enpirion, Max 10Tags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.