Sequencing regulated power to large ICs such as CPUs, FPGAs, and ASICs is a critical job that’s become increasingly complex as the number of power rails increases. The wrong power-up sequence can prevent a system from initializing properly and the wrong power-down sequence can cause data loss. If you’re facing a design with complex power-sequencing requirements, then the configurable Multi-Rail Power Sequencer and Monitor Reference Design based on an Intel® Max® 10 FPGA might be just the design solution you need. The Multi-Rail Power Sequencer and Monitor can simultaneously monitor and correctly sequence as many as 143 power rails by monitoring a combination of “power OK” (POK) digital signals and as many as 18 analog supply voltages, which should be more than adequate for just about any system design. The Multi-Rail Power Sequencer and Monitor also supports the PMBus 1.3.1 protocol, which is based on the I2C physical interface and used by many power-converter ICs and modules including many Intel® Enpirion® dc-dc stepdown converters. This power sequencer is a block-based reference design, as shown below, and you can remove any IP blocks that aren’t needed for your system design.
This reference design is fully described in a 41-page application note titled AN 896: Multi-Rail Power Sequencer and Monitor Reference Design.
You can download the Multi-Rail Power Sequencer and Monitor Reference Design here.
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