Meet 5G High Density I/O Goals through Software Optimization and Hardware Acceleration


Intel, Affirmed Networks, and Dell EMC have developed a proof of concept for high-performance Next-Generation Core Networks (NGCN). Together, the three companies have written and published a White Paper that presents a state-of-the-art solution for a commercial, standalone 5G core network (5GCN) that achieves 100 Gbps/CPU socket using a 100 GbE NIC plugged into a server based on an Intel® Xeon® Scalable processor. Smart load balancing using Intel® FPGA and CPU cache optimizations with Affirmed Networks’ 5G User Plane Function (UPF) enhances the software performance of 5GCN applications.

The growth in wireless and cellular services driven by numerous technological and market forces including 5G, edge computing, and the IoT require mobile operators to build new, highly available infrastructure that can scale efficiently to accommodate a massive number of connected devices and handle the expected exponential rise of data traffic, while accommodating different quality-of-service (QoS) levels as required by different use cases. Current network solutions use specialized network appliances based on proprietary hardware that simply aren’t sufficient to support future 5G needs.

Proprietary network hardware is expensive and relatively inflexible and presents the developer ecosystem with far too many challenges to permit efficient resource leveraging. Network functions virtualization (NFV) has emerged as a means of providing the necessary resource flexibility to ensure high utilization and sufficient programmability to accommodate these diverse 5G workload profiles.

NFV built on best-in-class x86 infrastructure provides optimal and cost-effective deployment. To further increase performance while preserving the form factor for these virtualized systems, Intel FPGAs deployed as accelerators can provide energy and cost savings. FPGA-accelerated solutions result in lower power consumption per bit and reduced latency compared to traditional solutions. This design approach allows fine-grained QoS characteristics across multiple, diverse network slices in deployed 5G networks.

The significant benefits of using Intel® FPGA-based Programmable Acceleration Cards (PACs) as hardware accelerators for communications networks include efficient scaling, increased throughput capacity, fast time to market, flexibility, and lower total cost of ownership (TCO). Intel PACs cleanly integrate FPGAs into the NFV life cycles and permit scheduling of accelerated workloads into OpenStack* services including Nova, Cyborg, and Neutron. As demand shifts and changes over time, the FPGAs in the Intel PACs can be reprogrammed, updated, and upgraded to optimally address the new requirements.

For example, leveraging a combination of aggressive software optimization in the user plane along with acceleration of NFVI and selected VNFs’ functionalities, and additional data center architectural enhancements can increase overall server performance for VNFs in cloud environments. The VNFs can be hosted within either a VM or a container and a single FPGA in an Intel PAC can be shared among multiple VNFs.

Using Intel PACs to implement NFVs provides the hardware and IP flexibility to support today’s popular workloads and can be programmed to support future workloads with the following benefits:

  • Improves bandwidth to meet ever-growing bandwidth and through demands
  • Enhances network performance
  • Programming and reprogramming capability adapts to different acceleration solution needs
  • Permits scaling to diverse and evolving applications
  • Augments the system with a flexible acceleration solution, increasing total system capabilities
  • Offers a more deterministic solution for total system performance and latency
  • Gains flexibility to accommodate evolving standards
  • Leverages acceleration of selected workloads to free system resources that can then be allocated to additional workloads
  • Achieves TCO goals
  • Fast time to market
  • Supports OpenStack orchestration
  • Leverages existing developer tools and libraries
    • Data Plane Developer Kit (DPDK)
    • Open Programmable Acceleration Engine (OPAE)
    • Intel Quartus® Prime Software and the Intel® FPGA SDK for OpenCL™ Application Developers


Note: This blog is based on a new White Paper titled “Enabling Communications Service Providers to Meet 5G High Density I/O Goals through Software Optimization and Hardware Acceleration.” To download the White Paper, please click here.



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Published on Categories 5G, Acceleration, PAC, QuartusTags , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.