Low-latency key-value store resides in FPGA SRAM, delivers data in a deterministic 500 nsec

Professor John Lockwood sits behind the wheel, piloting his slick electric roadster around a landscape filled with renewable energy sources: wind turbines, solar arrays, and a hydroelectric dam. He’s actually sitting at a simulation console in the Algo-Logic booth at the Supercomputing 2019 (SC’19) conference in the Denver Convention Center, watching the simulated world go by on a large-screen monitor as a simulated drone flies overhead and as other simulated cars pass by on a simulated roadway. All of the essential object data needed for rendering this simulation sits within a low-latency, key-value store (KVS) residing in the SRAM inside of an Intel® Stratix® 10 FPGA, which sits in an Intel® Programmable Acceleration Card (PAC) D5005. The Intel PAC D5005 is plugged into a server that supplies the information stored in the KVS to various local and remote, network-connected simulation-rendering PCs that serve as the user interface to this wide-area, connected-city simulation.

The low-latency KVS used in this demo is one of several FPGA-based IP blocks developed by Lockwood’s company, Algo-Logic, and this particular demo is taking place in Algo-Logic’s SC’19 booth. The advantage of placing a KVS in an FPGA’s SRAM is high-speed, deterministic access for critical real-time systems. In this demo, the real-time system is delivering electrical power to multiple customers from multiple renewable energy sources over a network of electrical transmission lines. Each customer draws a time-varying amount of power and each energy source generates a time-varying amount of power. For example, when Lockwood’s car stops at a car charger, it suddenly presents a 100 kilowatt load on the system. As the sun goes down, the solar-cell array generates less and less power, reaching zero when the sun sets.

The status of every energy source, every load, and every transmission line resides as data in the KVS. Any of these values can be accessed in 500 nsec and that’s a reliable, deterministic number. A real-time simulation needs that fast, deterministic access for a smooth simulation result. Other applications that need a low-latency, deterministic KVS include telecom directories, Internet Protocol (IP) forwarding tables, and de-duplicating storage systems. One common element shared by these applications is the presence of hundreds or thousands of distributed servers that all require real-time access to the data residing in the KVS. Without such a facility the store must be replicated in many locations. Having a central, low-latency KVS cuts the overhead required to duplicate the store.

If a wide-area energy system for a connected city doesn’t jibe with your idea of a system that needs a low-latency KVS with a 500 nsec access time, then perhaps you might consider a factory of the future, filled with individual machines and tools performing various manufacturing operations on work in progress (WIP) as it moves from tool to tool through a complex manufacturing process. Tracking the WIP, nailing the logistics to maximize throughput while meeting many complex and conflicting delivery requirements, identifying tools and equipment in need of maintenance or service through statistical process control, scheduling down time to provide that maintenance or service, scheduling an appropriately trained and certified technician to perform that maintenance or servicing, and finding bypass routes to circumvent tools temporarily taken out of service so that production is not adversely affected are all real-time, ongoing processes that rely on the same factory-wide database. This is a great application for a low-latency KVS. There are many other examples.


For more information about the Algo-Logic KVS IP, please contact Algo-Logic directly.


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Published on Categories Acceleration, Cloud, PAC, StratixTags , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.