Levyx Xenon Acceleration Framework runs on Intel® Xeon® CPUs, Intel® Optane™ SSDs, and FPGA-based Intel® programmable accelerator cards, speeds HFT model backtesting

Backtesting seeks to estimate the real-world performance of specific high-frequency trading (HFT) strategies or models as if they had been employed during a previous trading period. Levyx developed its hardware-accelerated Risk Analytics Acceleration Framework to help customers realize more profit from an HFT financial model by speeding up the calculations associated with that trading model. Backtesting these HFT financial models during their development explores the profitability of a new trading model by running the model’s computations over a year of historical price data for a given security. These computations are particularly data- and compute-intensive, which makes backtesting a great candidate application for hardware acceleration using FPGAs.

FPGAs can accelerate many kinds of mathematical calculations including backtesting. Faster backtesting computations allow brokerages, investment banks, and hedge funds to test and deploy more robust and profitable trading models more quickly across their electronic trading and risk-management systems, which in turn reduces financial risk and increases profitability.

The Levyx Risk Analytics Acceleration Framework is based on the company’s highly scalable, low-latency Xenon data-analytics processing engine, which Levyx developed to manage the retrieval, processing, and indexing of very large datasets. The Xenon engine bypasses conventional file-systems and kernel buffers and directly performs SSD-friendly I/O operations to reduce I/O latency and maximize I/O bandwidth for storage devices. In particular, the Xenon data analytics engine allows application programs to treat storage space on Intel® Optane™ NVMe SSDs like RAM, which significantly speeds operations.

The Xenon engine also uses just-in-time (JIT) compilation to generate analytics code on the fly and then executes that code on Intel® Xeon® CPUs for maximum efficiency and throughput with low latency. Optionally, the Xenon engine can push complex calculations to hardware accelerators such as the Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA to further increase performance.

For testing, Levyx created a demo with an 8 Tbyte dataset representing one year of trading data on the NASDAQ stock exchange. A sample financial model then calculated 10-minute moving averages over the year-long dataset and compared the most recent price tick to the moving average at each 10-minute interval. The financial model made trades when the last tick price was a specified distance away from the average based on a mean-reversion signal.

This demo traded synthetic stock, which is an options trading strategy that trades at-the-money call options and an equal number of at-the-money put options of the same underlying stock with identical expiration dates. Synthetic stock trading is a low-cost alternative to purchasing the stock outright, but this type of option-based trading strategy is computationally intensive. The backtesting demo application devoted more than 70% of its elapsed run time to the calculations while running on a CPU. Adding FPGA-based acceleration reduced the calculation overhead to just 30% and cut the overall run time significantly.

 

For many more details, see the White Paper titled “Why FPGA actually stands for “financial programming greatly accelerated,” available on the Intel® FPGA Acceleration Hub.

 

For more details about the Levyx Risk Analytics Acceleration Framework and the company’s Xenon data-analytics processing engine, please contact Levyx directly.

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.