Many workloads have inherent data parallelism which can be leveraged to achieve optimal performance. However, it is challenging to design data parallel programs and map them to different hardware targets. Data Parallel C++ (DPC++) is an open alternative for cross-architecture development, aiming to address this challenge. A session titled “Word-Count with MapReduce on FPGA, A DPC++ Example” at the upcoming ISC oneAPI Dev Summit, a two-day live virtual conference, discusses the MapReduce distributed programming model for large datasets and how to accelerate MapReduce processing using FPGAs and DPC++.
The tutorial will be presented by Dr. Yan Luo, a Professor in the Department of Electrical and Computer Engineering at the University of Massachusetts Lowell. Dr. Luo’s research spans computer architecture, machine learning and data analytics. He teaches undergrad and graduate courses on topics such as embedded systems and heterogeneous computing.
To register for the oneAPI Dev Summit (June 22-23) and Dr. Luo’s DPC++ tutorial (June 23), click here.
For more information about DPC++, see:
- Intel’s ‘One API’ Project Delivers Unified Programming Model Across Diverse Architectures
- Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!
- Free Webinar: Accelerate FPGA Programming using Data Parallel C++ (DPC++) and the Intel® oneAPI Base Toolkit with the Intel® FPGA Add-on
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