Learn to use Data Parallel C++ to accelerate MapReduce processing at this ISC oneAPI Dev Summit session on June 23

Many workloads have inherent data parallelism which can be leveraged to achieve optimal performance. However, it is challenging to design data parallel programs and map them to different hardware targets. Data Parallel C++ (DPC++) is an open alternative for cross-architecture development, aiming to address this challenge. A session titled “Word-Count with MapReduce on FPGA, A DPC++ Example” at the upcoming ISC oneAPI Dev Summit, a two-day live virtual conference, discusses the MapReduce distributed programming model for large datasets and how to accelerate MapReduce processing using FPGAs and DPC++.

The tutorial will be presented by Dr. Yan Luo, a Professor in the Department of Electrical and Computer Engineering at the University of Massachusetts Lowell. Dr. Luo’s research spans computer architecture, machine learning and data analytics. He teaches undergrad and graduate courses on topics such as embedded systems and heterogeneous computing.


To register for the oneAPI Dev Summit (June 22-23) and Dr. Luo’s DPC++ tutorial (June 23), click here.



For more information about DPC++, see:




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Published on Categories Acceleration, DPC++Tags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.