Indoor picocells will play an extremely vital role in achieving ambitious 5G cellular service goals in terms of of coverage, capacity, and ubiquitous services. These goals will be achieved primarily through network densification. Intel has been working with customers and partners to develop many end-to-end solutions for the 5G market, which includes indoor picocells.
The Intel picocell end-to-end solution is based on FlexRAN, which is an end-to-end Intel reference architecture for implementing software-based radio stations that can sit on any part of the wireless network from edge to core. A FlexRAN platform solution performs the entire 4G and/or 5G layer 3, 2, and 1 processing. Intel Xeon Scalable processors are used to implement layers 3 and 2 and some of layer 1, and Intel FPGAs are used to accelerate the remainder of layer 1 and the fronthaul connectivity.
This flexible, reprogrammable, end-to-end, 5G picocell reference platform includes three main elements:
- A baseband unit (BBU)
- A radio hub (RHUB)
- A remote radio unit (RRU)
The 5G BBU reference design implements L3, L2 and L1 on commercial off-the-shelf (COTs) hardware and consists of a server based on an Intel® Xeon D processor paired with an Intel FPGA PAC N3000 accelerator card. The Intel FPGA and Intel® NIC on the Intel PAC are used to implement both fronthaul acceleration and channel coding. The Intel PAC card can implement any fronthaul standard (IEEE1914.3, eCPRI, and xRAN/ORAN) and lower-layer channel-coding functions such as Turbo coding for 4G networks and LDPC/Polar channel coding for 5G networks.
The RHUB functions as a fronthaul switch, which efficiently aggregates and transports signals and data from multiple RRUs. The RHUB can also, optionally provide baseband acceleration because it incorporates computing resources. In addition, the RHUB reduces the number of links needed to connect the BBU with the multiple RRUs. The RHUB in the Intel picocell reference design can support as many as twelve cells with 4T4R (four transmit, four receive) MIMO (multiple input, multiple output) antenna configurations or as many as nine cells with 16T16R (sixteen transmit, sixteen receive) MIMO antenna configurations. It can also support as many as three cells with multiple, 100MHz, millimeter-wave links for 5G networks.
The RRU in the Intel 5G picocell reference platform is based on the Intel® Arria® 10 FPGA and is capable of implementing digital up conversion (DUC), digital down conversion (DDC), crest-factor reduction (CFR), and digital predistortion (DPD) in real time for multiple antennas. The Intel Arria 10 FPGA in the RRU also implements the JESD204B/C interface needed to connect to high-speed ADCs and DACs. In addition, Intel® eASIC structured-ASIC products offer cost and power reduction alternatives for RRU design.
MWC Shanghai 2019, June 26 to 29
Intel and some of its 5G ecosystem partners will be demonstrating working implementations of these BBU, RHUB, and RRU reference designs in the Intel 5G picocell reference design later this month at MWC Shanghai 2019.
Meanwhile, Intel has published a Solution Brief titled “Enabling 5G Fronthaul.” Click here to download a copy.