Interested in using Intel® oneAPI Toolkit with FPGAs to accelerate your code? Free 6-hour Webinar. Register now

Intel® oneAPI Beta Toolkits will deliver uncompromised software performance for diverse workloads across multiple architectures, including Intel® CPUs and Intel® FPGAs, using Data Parallel C++ (DPC++). You can learn how to use these powerful new software-development tools in a free, 6-hour Webinar being held on May 19. This course will teach you how to use the Intel oneAPI Toolkits to target an Intel FPGA accelerator. During this class you’ll learn how to:

 

  • Write DPC++ code to target an Intel FPGA accelerator
  • Understand the flow needed to target DPC++ code to an FPGA
  • Understand how your code is compiled into an FPGA design incorporating a Custom Compute Pipeline
  • Understand and be able to write your kernel scope code as a task
  • Examine an FPGA optimization report and analyze performance bottlenecks
  • List several techniques to optimize your kernel scope code

 

The only prerequisite for this class is a basic understanding of C++.

This will be a virtual class with a live instructor who will answer your chat questions in real time (time permitting). There is no need to pre-install the tools. This class will utilize the Intel® DevCloud via a web interface with JupyterLab.

Click here to register.

 

Notices and Disclaimers

Intel technologies may require enabled hardware, software or service activation.

No product or component can be absolutely secure.

Your costs and results may vary.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

 

Published on Categories Acceleration, oneAPITags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.