Interested in using FPGAs for Datacenter Acceleration? Sign up for a free August 29 Webinar

FPGAs excel at accelerating compute-intensive workloads in data centers. Now you can learn about the possibilities for workload acceleration in a free Intel Webinar titled “Using FPGAs for Datacenter Acceleration.” In this Webinar, you’ll learn how how you can deploy deep-learning inference tasks on FPGAs using the Intel® Distribution of OpenVINO™ toolkit and the Intel FPGA Deep Learning Acceleration Suite. You’ll also learn to use the Acceleration Stack for Intel Xeon® CPU with FPGA to develop and deploy workload optimizations on Intel Programmable Acceleration Cards (PACs) including the Intel PAC with Arria® 10 GX FPGA and the Intel FPGA PAC D5005 based on the Intel Stratix® 10 FPGA.

This Webinar, one of a series of free Intel AI Webinars, takes place on August 29 and will be taught by Intel Application Engineer Steven Elzinga, who focuses on FPGA-based deep learning acceleration techniques.

For more information about the Webinar and to sign up, click here. You’ve got ten days.

Tick, tock.

For more information about using FPGAs for AI applications, check out the Intel® FPGA Acceleration Hub.

Published on Categories AI/ML, PAC, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.