Intel® Stratix® 10 DX FPGAs Accelerate Intel® Xeon® Scalable Processors in Servers and High-End Embedded Systems

Hardware acceleration for servers is becoming increasingly common because these accelerators can perform calculations faster and more efficiently than the same computations running in software. The recently announced, high-performance Intel® Stratix® 10 DX FPGA family has been designed specifically to provide FPGA-based hardware acceleration and memory expansion for next-generation server systems including servers based on selected Intel® Xeon® Scalable processors that are compatible with UPI mesh networks.

FPGAs serve as excellent foundations for hardware accelerator designs because of their massive parallelism and dynamically reprogrammable datapaths, which can be configured to exactly match the computational needs of specific application workloads. Their versatility enables the provisioning of faster, more power-efficient, lower-latency services, which lower total cost of ownership and maximize compute capacity within a data center’s power, space, and cooling constraints. However, the communications between the server processors and the hardware accelerator must be streamlined to extract maximum benefit from the accelerator hardware.

Diverse server workloads can benefit from hardware acceleration. These specialized workloads include:

  • Cloud Disaggregation
  • Financial/HPC
  • Encryption/Decryption
  • Compression/Decompression
  • Video Transcoding
  • Storage
  • Genomics
  • Database Acceleration/Data Analytics
  • General Cloud-Based Compute Acceleration

 

Intel Stratix 10 DX FPGAs incorporate a number of specific features that make them ideal for use for these applications, including:

  • Multiple coherent Intel® Ultra Path Interconnect (Intel® UPI) ports that support direct, peer-to-peer connection to selected Intel Xeon Scalable processors
  • Multiple PCIe Gen4 interface ports (PCIe Gen3-capable as well) with advanced virtualization features
  • A new soft-IP memory controller for select Intel Optane DC Persistent Memory DIMMs, with a maximum capacity of 4 Tbytes of non-volatile memory per FPGA.
  • High Bandwidth Memory 2 (HBM2) 3D DRAM stacks that deliver extremely high memory bandwidth

 

These unique features permit Intel Stratix 10 DX FPGAs to act as peers on the Intel UPI network, at the very core of server systems, and to deliver high bandwidth and low latency in both hardware-acceleration and memory-expansion roles through the integrated PCIe Gen4 and Intel UPI interfaces. For more detail, see the new Intel White Paper titled “Intel® FPGAs Accelerate Intel® Xeon® Scalable Processors in Servers and High-End Embedded Systems.”

 

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Published on Categories Acceleration, Cloud, HPC, Storage, Stratix, VideoTags , , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.