The P-tile incorporated in the newly announced Intel® Stratix® 10 DX FPGA is the first and currently the only FPGA component-level device listed in the PCI-SIG Integrators List for PCI Express 4.0 (PCIe Gen4). You’ll find it in the “Components: Endpoints” section. The P-tile implements the Intel Stratix 10 DX FPGA’s PCIe Gen4 x16 interface. (Note: the P-tile – and therefore the Intel Stratix 10 DX FPGA – implements the PCIe 4.0 Root Port function as well.)
Admission to the PCI-SIG Integrators List came after a very successful PCI-SIG Compliance Workshop held earlier this year in August. At this workshop, a PCIe 4.0 board based on the Intel Stratix 10 DX FPGA successfully interoperated with twelve out of twelve other PCIe 4.0 compliant vendor products including CPUs, ASSPs, and test equipment.
Normally, this blog does not discuss the tiles incorporated into Intel FPGAs because developers are more interested in the I/O and transceiver ports made possible by these tiles. However, in this case, the PCI-SIG Integrators List explicitly says that the listed component is the P-tile used in the Intel Stratix 10 DX and Intel® Agilex™ FPGAs. That’s a reminder that the Intel EMIB and tile technologies used to construct Intel Stratix 10 FPGAs are the same technologies used to construct Intel Agilex F-Series FPGAs, and that is what earned the Intel Agilex FPGA a place on the PCI-SIG Integrators List for PCIe 4.0 compatibility.
For more information about the new Intel Stratix 10 DX FPGA, see:
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