Back in 1965, in his landmark article titled “Cramming more Components onto Integrated Circuits,” Gordon Moore noted that, “…It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” The budding semiconductor industry had other ideas and has taken a wild ride down the scaling slopes, going from micron-sized features, to sub-micron features, and now into the low nanometer feature-size range over the the last four and a half decades. The innovations enabled by these achievements in monolithic scaling that include a billion-fold increase in the number of transistors on a chip are truly staggering, but for various reasons, multi-chip devices have been present all along the way as well.
Multi-chip devices and the ideas surrounding the incorporation of reusable chiplets into Systems in Packages (SiPs) are increasingly compelling at the single-digit nanometer scales that can be manufactured today. While aggressive device scaling has taken bulk CMOS and now tri-gate logic processes to the lithographic limits in the name of device density for core logic functions, other functional types such as analog signal processing and analog I/O, digital and high-speed serial I/O, semiconductor and advanced memory technologies, optical functions, and certain other types of silicon IP are better suited to fabrication with other types of IC process technologies.
The adoption of SiP and chiplet technologies permits faster device development, lowers integration costs, and improves performance in many situations. One of the requirements needed to enable a vibrant and growing chiplet ecosystem is a chip-to-chip interconnect standard that permits easy connection between chips and chiplets in a SiP. Intel has developed a chiplet-to-chiplet (or die-to-die) interconnect standard called the Advanced Interface Bus (AIB) and has made the use of this standard royalty-free to enable a broad ecosystem of chiplets, design methodologies, service providers, foundries, packaging, and system vendors. DARPA has adopted the AIB standard for its Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program, which focuses on modular design and the development reusable silicon IP blocks in the form of physical chiplets. Intel presented a paper titled “A SiP Standard for Reusable Chiplet Enabled Platforms” describing this standard at the Government Microcircuit Applications & Critical Technologies conference (GOMACTech 2019) held in Albuquerque, New Mexico earlier this year.
AIB is not merely a conceptual standard awaiting industry validation and adoption. Intel employs this standard in the daily manufacture of shipping, production devices such as the many members of the extended Intel® Stratix® 10 FPGA family. All members of the Intel Stratix 10 GX, SX, TX, and MX FPGA and SOC FPGA families employ chiplets (which Intel calls “tiles”) and AIB interconnect technology. Further, the recently announced Intel® Agilex™ FPGA family similarly leverages AIB, chiplet, and SiP technologies.
Figure 1 shows a photo of a lidless Intel Stratix 10 MX FPGA that reveals how Intel uses AIB interconnect technology to couple an Intel Stratix 10 FPGA die to four transceiver tiles and two HBM2 stacked-DRAM tiles to create the SiP. This chiplet-based assembly technique also makes use of the Intel Embedded Multi-die Interconnect Bridge (EMIB) technology to carry the AIB interface between the FPGA die and each chiplet.
Figure 1: The Intel Stratix 10 FPGA family employs AIB interconnect to build a SiP from an FPGA die, four transceiver tiles, and two HBM2 stacked-DRAM tiles.
Use of AIB and EMIB technologies and chiplets allow Intel to develop SiPs that closely match intended applications far more quickly. Thus AIB is already proven technology that’s being used in volume manufacturing to deliver “More than Moore” manufacturing advances.
For more information about Intel’s use of AIB and 3D manufacturing technologies to produce Intel Stratix 10 and Intel Agilex FPGAs, see “Enabling Next-Generation Platforms Using Intel’s 3D System-in-Package Technology.”