Intel® Quartus® Prime software v21.1 adds new many features and improvements to aid FPGA development and debug. Available now

The latest release of Intel® Quartus® Prime software v21.1 introduces new intuitive features and improvements that make it easier for you to design with Intel® FPGAs, including the new Intel® Agilex™ FPGAs. These new features and improvements include:

  • Improvements for Intel® Agilex™ FPGA power, performance, runtime, memory, and logic utilization†
  • New and improved Design Assistant design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC)
  • New timing features including hierarchical grouping of design rule checking (DRC), rule tagging and filtering, and a DRC waiver mechanism
  • New ease-of-use reports for static timing analysis, design closure, synthesis, and undefined entities
  • Additional cross-probing and runtime improvements for reports that allow you to locate SDC constraints in a file
  • Faster ECO compilation for post-fit tap targets in Signal Tap II Logic Analyzer†
  • A new Flow-Resume feature
  • Improved GUI display compatible with higher resolution monitors
  • Accelerated remote debug over Ethernet and PCIe connections (as opposed to JTAG) using an instantiated Nios® II processor
  • A new feature that allows you to mark signals for debug (Beta) during RTL code development
  • Updates to embedded development software and other development tools including:
    • BSP Editor Added to Platform Designer
    • Support for U-Boot 2020.10
    • ARM Trusted Firmware v2.4.0
    • Linux LTS Kernel v5.4, Mainline Kernel v5.11


The new Intel Quartus Prime development software version 21.1 is available for immediate download. Click here.



Notices & Disclaimers


† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit

Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available ​updates.  See backup for configuration details.

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Published on Categories Agilex, QuartusTags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.