The Intel® eASIC™ Diamond Mesa structured ASIC technology now has a name: Intel eASIC N5X

The Intel® eASIC™ N5X structured ASIC is the industry’s newest and most capable structured ASIC family. This product cuts power consumption and achieves higher performance relative to FPGAs, and ultimately enables faster TTM relative to ASICs. Intel eASIC N5X devices are the first structured ASICs from Intel that leverage Intel innovations such as the hard processor system and security features derived from and compatible with the Intel Agilex FPGA. Security features in the Intel eASIC N5X structured ASIC family include the secure device manager used in Intel Agilex FPGAs, which manages boot, authentication, and anti-tamper features.

Core power consumption for Intel eASIC N5X devices is as much as 50% lower than for Intel Agilex FPGA devices, which eases thermal constraints and allows designers to increase performance in the same thermal envelope. When compared to ASICs, Intel eASIC N5X devices lower total cost of ownership by delivering faster TTM and lower NRE. This new product family targets a broad range of workloads including 5G wireless base stations and radios, cloud acceleration, storage, AI inference processing, and many edge applications.

These Intel eASIC N5X structured ASICs leverage the Diamond Mesa SOC technology discussed at Mobile World Congress earlier this year. (See “Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals?”)

 

For more information about the Intel eASIC N5X structured ASIC family, see the associated Intel News Byte and click here.

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.