Intel announces open oneAPI initiative and development beta release with Data Parallel C++ language for programming CPUs, GPUs, FPGAs, and other accelerators

On Sunday and the Intel HPC Developer Conference in Denver during his keynote presentation, Intel’s senior vice president, chief architect, and general manager of architecture, graphics, and software Raja Koduri announced the oneAPI initiative, the product beta release, and the Data Parallel C++ (DPC++) programming language that allows developers to target CPUs, GPUs, FPGAs, and other hardware accelerators with one source code document. (See “Intel Unveils New GPU Architecture with High-Performance Computing and AI Acceleration, and oneAPI Software Stack with Unified and Scalable Abstraction for Heterogeneous Architectures.”) The oneAPI initiative is part of Intel’s data-centric strategy and is aimed at substantially easing the development of application code with a laser focus on the convergence of AI and HPC, which are the top trends driving today’s most ambitious industrial innovations and scientific breakthroughs. (Click here for the Intel oneAPI developer’s page.)

The Intel oneAPI beta release supports two different programming styles – direct programming through DPC++ and API-based programming – to provide an efficient unified development model that can offer full, native code performance across a range of heterogeneous processing hardware. The oneAPI initiative – specifications are available at the Web site, along with a call for industry and community comment – is a cross-industry, open, standards-based, unified and simplified programming model for application development across heterogeneous processing architectures including CPUs, GPUs, FPGAs, and other hardware accelerators —with an eye towards enabling faster application performance, fostering more developer productivity, and empowering greater innovation.

The oneAPI industry initiative also represents a software development style that shifts away from single-architecture, single-vendor programming models in favor of scalable heterogeneous architectures. Consequently, the oneAPI initiative encourages the development of compatible oneAPI implementations in the form of toolkits, plug-ins, and add-ons for heterogeneous architectures across the broad ecosystem.

DPC++ is built upon the ISO C++ and Khronos SYCL standards. It extends these standards by providing explicit parallel constructs and offload interfaces to support a broad range of heterogeneous computing architectures and processors, including CPUs, GPUs, FPGAs, and other hardware accelerators. This flexibility is a cornerstone of Intel’s xPU strategy: to offer a diverse mix of heterogeneous processing architectures that uniquely support diverse AI and HPC workloads. Here’s a video that explores DPC++ in a little more detail:



The oneAPI concept also includes a set of APIs spanning several domains that can benefit from acceleration, including an interface for deep learning; general libraries for linear algebra math, video, and media processing; and others. The oneAPI initiative is just the start of a long software journey – a journey aimed at simplifying software development across diverse data-centric processing architectures.

The initial beta release of the Intel version of oneAPI and the DPC++ programming language are available as tailored toolkit downloads and on the Intel Developers Cloud. This beta release allows developers to learn about oneAPI, to write and test code, and to experiment with the oneAPI environment and the DPC++ language using Intel® CPUs, GPUs, FPGAs.

Currently, the Intel oneAPI beta release supports FPGAs through a download of the Intel® FPGA Add-On for oneAPI Base Toolkit. Here’s a video that explains the use of oneAPI and DPC++ with Intel FPGAs in more detail:





Legal Notices and Disclaimers:

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at

Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.

Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate.

Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

Other names and brands may be claimed as the property of others.


Published on Categories Uncategorized
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.