Intel announces Intel® Stratix® 10 GX 10M FPGA, world’s highest capacity with 10.2 million logic elements. Targets ASIC Prototyping and Emulation Markets

By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel Network and Custom Logic Group


Multiple customers have already received operational samples of the new Intel® Stratix® 10 GX 10M FPGA, the world’s densest FPGA with 10.2 million logic elements (LEs), and the device is now in production. This extremely dense FPGA is based on the existing Intel Stratix 10 FPGA architecture and Intel’s advanced Embedded Multi-die Interconnect Bridge (EMIB) technology. In the case of this new Intel Stratix 10 GX 10M FPGA, EMIB technology stitches two high-density Intel Stratix 10 GX FPGA core fabric die (with a capacity of 5.1 million LEs per die) along with appropriate I/O tiles. The Intel Stratix 10 GX 10M FPGA with 10.2 million LEs is approximately 3.7x denser than the Intel Stratix 10 GX 1SG280 FPGA, previously the densest member of the Intel Stratix 10 device family. Intel’s EMIB technology is just one of many IC process technology, manufacturing, and packaging innovations that have allowed Intel to design, manufacture, and most importantly ship what is currently the world’s highest density (compute capacity) FPGA.


The Intel Stratix 10 GX 10M FPGA with a total of 10.2 million logic elements (LEs) is the first Intel FPGA to use EMIB technology to logically and electrically bond two FPGA fabric die together.


One market in particular has a critical interest in always using the largest available FPGAs: the ASIC prototyping and emulation market. There are several vendors offering commercial, off-the-shelf (COTS) ASIC prototyping and emulation systems participating in this market. Access to the largest available FPGAs for use in ASIC emulation and prototyping systems is a substantial competitive advantage for these vendors.

In addition, many large semiconductor companies, including Intel, develop their own custom prototyping and emulation systems and use them to verify their largest, most complex, and therefore riskiest ASSP and SoC designs prior to tape out. ASIC emulation and prototyping systems can help design teams to lower this design risk by a significant amount. Consequently, Intel FPGAs including the Intel Stratix 10 FPGAs and even much earlier Stratix® III, Stratix IV, and Stratix V devices have been used as the foundation in many of these emulation and prototyping systems for more than a decade.

ASIC emulation and prototyping systems support many activities associated with IC and system development including:


  • Algorithm development using real hardware
  • Early SoC software development prior to the chip’s manufacture
  • RTOS verification
  • Corner-case condition testing for both hardware and software
  • Regression testing on successive design iterations


Emulation and prototyping systems are designed to save semiconductor vendors millions of dollars by helping them identify and eradicate costly hardware and software design bugs before the chips are fabricated. It’s far more costly to fix hardware design bugs after a chip has been manufactured – it usually requires an expensive respin of the design. It’s even more costly to fix these problems once equipment has been manufactured and shipped to end customers. Because the risk is so high and the potential savings are so large, these prototyping and emulation systems deliver real, tangible value to IC design teams. As a result, use of these systems has become widespread because no design team leader can dare ignore such a prudent verification investment when the economic stakes are so high.

Use of the largest FPGAs allows big ASIC, ASSP, and SoC designs to fit into the fewest number of FPGA devices. The Intel Stratix 10 GX 10M FPGA is merely the latest in a line of large FPGAs used for these applications. This new Intel Stratix 10 FPGA enables the development of emulation and prototyping systems that can accommodate digital IC designs consuming hundreds of millions of ASIC gates. The 10.2 million LE Intel Stratix 10 GX 10M FPGA is already supported in the Intel® Quartus® Prime Software Suite with novel, specialized IP that explicitly supports ASIC emulation and prototyping.

The Intel Stratix 10 GX 10M FPGA is the first Intel FPGA to use EMIB technology to logically and electrically bond two FPGA fabric die together to achieve the 10.2 million LE density. For this device, tens of thousands of connections link the two FPGA fabric die through multiple EMIB die, resulting in a high-bandwidth connection between the two monolithic FPGA fabric die.

Previously, Intel has used EMIB technology to connect I/O and memory tiles to FPGA die, which has resulted in the large and growing family of Intel Stratix 10 FPGAs. For example, Intel Stratix 10 MX devices incorporate either 8 or 16 Gbytes of EMIB-connected, 3D stacked HBM2 SRAM tiles. The recently announced Intel Stratix 10 DX FPGA incorporates EMIB-connected P tiles that provide PCIe 4.0 compatibility. (See “Intel® Stratix® 10 DX FPGA is first (and only) FPGA on the PCI-SIG System Integrators List for PCIe 4.0.”)

The P tile used in the Intel Stratix 10 DX FPGA is the first component-level device to appear on the PCI-SIG System Integrators List for PCIe 4.0. The same P tile is also tightly integrated into the recently announced Intel® Agilex™ FPGA, giving that device PCIe 4.0 compatibility as well. (See “Need PCIe Gen4 x16 version 1.0 capability with full PCI-SIG compliance in an FPGA today? Intel® Agilex™ FPGAs can deliver.) The P tile used in both the Intel Stratix 10 DX and Intel Agilex FPGAs is yet another excellent example of how advanced manufacturing and production technologies such as EMIB have allowed Intel to bring a range of new products to market, and into full production, quickly.

Perhaps most important, the semiconductor and packaging technologies used to create the Intel Stratix 10 GX 10M FPGA are not simply targeted at building the world’s biggest FPGAs. That’s a (rather important) side benefit, but it’s not the main point.

Here is the main point:

These technologies allow Intel to build just about any sort of device imaginable by incorporating different semiconductor die – FPGAs, ASICs, eASIC structured ASICs, I/O tiles, 3D stacked memory tiles, photonic devices, etc. – into a System in Package (SiP) to meet specific customer needs. Combined, these advanced technologies constitute a unique, innovative, and very strategic Intel advantage.


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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.