Intel and Partners Demo End-to-End 5G Picocell Solution at MWC Shanghai


Picocells are critical network elements that will be required for low-cost densification of 5G networks. Densification will create wireless networks that are more agile, more elastic, and more intelligent while delivering better network performance, at lower cost, and with better energy efficiency. Last month at MWC Shanghai, Intel and some of its 5G partners demonstrated an end-to-end picocell solution for cellular networks based on three main components:

  • A baseband unit (BBU) containing two Intel® Xeon® processors and two Intel N3000 FPGA Programmable Acceleration Cards (PACs), which are based on Intel Arria® 10 FPGAs.
  • A radio hub (rHUB) used for cell merging in some exchanges, and for optional baseband processing and interface conversions.
  • A remote radio unit (RRU), which implements the RF reception and transmission.

One of the Intel N3000 PACs in the BBU implements real-time Turbo encoding and transcoding for 4G communications and real-time LDPC encoding and decoding for 5Gcommunications. The other BBU PAC performs pre-processing and some interface conversions for the rHUB.

The RRU in the Intel picocell solution is also based on an Intel Arria 10 FPGA, which performs numerous real-time, RF-related tasks including digital up conversion (DUC), digital down conversion (DDC), crest-factor reduction (CFR), and digital predistortion (DPD) in real time for multiple antennas. The Intel Arria 10 FPGA in the RRU also implements the JESD204B/C interface needed to connect to high-speed ADCs and DACs.

The Intel end-to-end 5G picocell solution also includes the possibility of using Intel® eASIC structured-ASIC products for cost and power reduction when the design enters the volume-deployment phase.

Here’s a video of the Intel end-to-end picocell solution from last month’s MWC Shanghai event:




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Published on Categories 5G, Arria, Communications, NetworkingTags , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.