Intel and DARPA announce SAHARA program to develop secure, reliable, domestic source of Structured ASICs

Intel and the U.S. Defense Advanced Research Projects Agency (DARPA) have just announced a three-year partnership to advance the development of domestically manufactured structured ASIC platforms through a partnership program named “Structured Array Hardware for Automatically Realized Applications” (SAHARA). The SAHARA program’s goal is to enable the design of custom chips that include state-of-the-art security countermeasure technologies, made available through a reliable, secure, domestic source of leading-edge semiconductors.

As the sole U.S.-based manufacturer of advanced semiconductors, Intel will provide supply-chain security to the SAHARA partnership through manufacturing, assembly, and test facilities located in the U.S. The company currently offers several Intel® eASIC structured ASIC device families.

“We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process,” said José Roberto Alvarez, senior director of the CTO Office in the Intel Programmable Solutions Group.

Intel will collaborate with collaboration with the University of Florida, Texas A&M and University of Maryland to improve the security of these structured ASICs through the entire design/verify/test/manufacture cycle. Intel will develop security countermeasure technologies to enhance protection of data and intellectual property against reverse engineering and counterfeiting. Meanwhile, the university teams will employ rigorous verification and validation techniques and will develop new attack strategies to test the security of these devices. These security countermeasure technologies will then be integrated into Intel’s structured ASIC design flow.

 

For more information about the SAHARA program announcement, see “Intel, DARPA Develop Secure Structured ASIC Chips Made in the US”.

 

For more information about Intel eASIC N5X devices, see “The Intel® eASIC™ Diamond Mesa Structured ASIC technology now has a name: Intel eASIC N5X”.

 

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.