Improve NFV Infrastructure performance with Segment Routing over IPv6 using the Intel® FPGA PAC N3000

Segment Routing (SR) transforms the way networking infrastructure handles packets to achieve better network performance. It’s useful at the Internet’s core and within or between data centers. SR is a simpler way to control networks that uses source routing to pre-program packet routes, to pre-schedule packet processing, and to implement traffic-engineering policies. SR can be used in Multiprotocol Label Switching (MPLS) and IPv6 data planes, employed respectively in telecommunications and networking systems.

Network Functions Virtualization (NFV) and Software Defined Networking (SDN) equipment and systems suppliers are increasingly realizing that standard network interface card (NIC) products may exhibit performance limitations when supporting emerging NFV/SDN workloads. Overcoming these performance limitations for SR applications may require more loading of server compute resources, which reduces the amount of resources available for implementing the actual Virtual Network Functions (VNFs). Even if this additional networking overhead is acceptable, the additional workload may cause overall system performance to be less predictable than when these networking functions are realized in hardware.

Intel FPGA acceleration solutions allow offloading of specific, low-level network functions such as SR to hardware, increasing data-path performance and improving predictability by saving CPU cores and cycles. These reclaimed CPU server resources are then available to execute VNFs and other workloads.

The Intel® FPGA Programmable Accelerator Card (PAC) N3000, an FPGA-based solution, can be programmed to handle almost any type of functionality – including networking functions – thus improving network and server performance.

HCL Technologies and Intel have prepared a White Paper titled “Segment Routing Over IPv6 Acceleration Using Intel® FPGA Programmable Acceleration Card N3000” that describes a solution to hardware-based SR using FPGA technology to improve network performance. Click here and scroll down to the SRV6 entry in the table to download the White Paper.


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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.