IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs

Time Sensitive Networking (TSN) is the IEEE 802.1 standard for deterministic packet transmission and handling over Ethernet networks. It is a set of evolving IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections; provides precise time synchronization of network nodes using synchronized, distributed local clocks; and serves as the network foundation for smart factories, Industry 4.0, and Intelligent Internet of Things (IIoT) applications. Intel is now offering special TSN versions of three Cyclone® V SoC FPGAs that include TTTech Industrial’s TSN Edge IP Solution with both an IP core and the embedded software required to build a TSN switch. There are no up-front license fees, no per-unit royalty reporting, and no protracted negotiations for the TTTech Industrial IP or software when the Cyclone V SoC FPGAs are purchased through Intel or its authorized distributors.

Three Cyclone V SoC FPGAs are available packaged with the TTTech Industrial TSN Edge IP solution:

  • Cyclone V SE SoC FPGA, U484 package (19mm), OPN: 5CSEBA6U19I7NTS
  • Cyclone V SE SoC FPGA, U672 package (23mm), OPN: 5CSEBA6U23I7NTS
  • Cyclone V SX SoC FPGA, U672 package (23mm), OPN: 5CSXFC6C6U23I7NTS


For more details including ordering instructions, click here.

For more information on implementing and using TSN in Intel FPGAs, see “Time Sensitive Networking: From Theory to Implementation in Industrial Automation.”

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Published on Categories Cyclone, NetworkingTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.