HPE now delivering ProLiant dL380 Gen10 Servers with optional Intel® D5005 Programmable Accelerator Card based on Intel Stratix® 10 FPGAs

Hewlett Packard Enterprise (HPE) is now shipping HPE ProLiant DL380 Gen10 servers with an optional Intel FPGA Programmable Acceleration Card (PAC) D5005 for workloads that can benefit from FPGA-based acceleration. Offering the Intel FPGA PAC D5005 as an option for its servers allows HPE to simplify ordering for its customers, streamlines system integration, and assures interoperability.

Bill Mannel, HPE’s vice president and general manager for HPC and AI, said:

“The HPE ProLiant Gen10 server family is the world’s most secure, manageable and agile server platform available on the market today. By integrating the Intel FPGA PAC D5005 accelerator into the HPE ProLiant DL380 Gen10 server, we are now delivering optimized configurations for an increasing number of workloads, including AI inferencing, big data and streaming analytics, network security and image transcoding.”

The Intel FPGA PAC D5005 is based on an Intel Stratix® 10 FPGA and offers more logic, memory, and networking capability than Intel’s previous PACs – which results in faster inline and lookaside workload acceleration for server-based applications.


HPE ProLiant DL380 Gen10 server and Intel FPGA PAC D5005


Developers can use the Intel Acceleration Stack, which includes acceleration libraries and development tools, to boost application performance.

Initial accelerated workloads specifically developed for the Intel FPGA PAC D5005 include:


For more information about the HPE ProLiant DL380 Gen10 server, please contact HPE directly.

For more information about the accelerated workload applications in this story, please contact the application vendors directly.



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Published on Categories Acceleration, Cloud, StratixTags , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.