Half-height, half-length PCIe Gen4 x16 card from Hitek Systems features 200G Ethernet port and incorporates Intel® Agilex™ FPGA for breakthrough performance

Hot on the heels of news about the Intel® Agilex™ FPGA’s breakthrough performance and power numbers — see “Breakthrough FPGA News from Intel” — Hitek Systems has announced a low-profile PCIe card based on the Intel Agilex AGF 014 FPGA. It is the first half-height, half-length PCIe FPGA card to support 200G PAM4 Ethernet and PCIe Gen4 x16, which means the card can support full-speed, 200 Gbps wire-to-host communications from its zQuad Small Form-factor Pluggable Plus (zQSFP+) optical cage to its PCIe edge connector, all supported by the on-board Intel Agilex FPGA’s high-performance programmable logic fabric and I/O. Hitek offers soft IP for 200G, 100G, and 50G PAM4 and 40G NRZ Ethernet ports. One 200G or four 50G soft Ethernet IP cores (encompassing MAC, PCS, and FEC blocks) from Hitek consume less than 20% of the on-board Intel Agilex FPGA’s resources.

The Hitek PCIe Gen4 card also incorporates 12 or 24 Gbytes of on-board DDR4 SDRAM in three banks directly driven by the FPGA and 16 Gbytes of eMMC Flash memory. One DDR4 SDRAM bank is routed to the 64-bit, quad-core Arm Cortex-A53 MPCore hard processor system (HPS) built into the Intel Agilex FPGA.

 

Half-height, half-length PCIe Gen4 x16 card from Hitek Systems incorporating an Intel® Agilex™ FPGA

 

The card is well suited to SmartNIC workloads and can be deployed in vRAN, ORAN, and 5G applications. It can also operate as a programmable accelerator in server systems to accelerate numerous data center workloads including real-time analytics, machine learning and AI, computational storage, database and search acceleration, and FinTech computations.

Hitek Systems has extensive experience stretching back more than two decades in designing boards and systems based on Intel® FPGAs.

 

For more information about the new Hitek PCIe Gen4 card based on the Intel Agilex FPGA, click here.

 

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.